PEF20525 INFINEON [Infineon Technologies AG], PEF20525 Datasheet - Page 124

• Manufacturer Part Number: PEF20525
• Description: 2 Channel Serial Optimized Communication Controller for HDLC/PPP
• Manufacturer: INFINEON [Infineon Technologies AG]

Data Sheet
Register 12
CPU Accessibility:
Reset Value:
Offset Address:
typical usage:
RDTB
RDRB
RDTA
RDRA
Bit
RDTB
7
Reset DMA Transmit Channel B
Reset DMA Receive Channel B
Reset DMA Transmit Channel A
Reset DMA Receive Channel A
Self-clearing command bit.
These bits bring the external DMA support logic to the reset state:
bit=’0’
bit=’1’
DCMDR
DMA Command Register
6
0
read/write
00
0C
written by CPU, evaluated by SEROCCO-H
H
H
RDRB
No reset is performed.
Reset is performed.
DMA Controller Reset Command Bits
5
5-124
4
0
RDTA
3
Register Description (DCMDR)
2
0
RDRA
1
PEB 20525
PEF 20525
2000-09-14
0
0