P82B96TD/S900 NXP [NXP Semiconductors], P82B96TD/S900 Datasheet

P82B96TD/S900

Manufacturer Part Number

P82B96TD/S900

Description

Dual bidirectional bus buffer

Manufacturer

NXP [NXP Semiconductors]

Datasheet

1.P82B96TDS900.pdf (32 pages)

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Bonase Electronics (HK) Co., Limited

Part Number:

P82B96TD/S900

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2 898

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1. General description

2. Features

The P82B96 is a bipolar IC that creates a non-latching, bidirectional, logic interface

between the normal I

For example, it can interface to the 350 A SMBus, to 3.3 V logic devices, and to 15 V

levels and/or low-impedance lines to improve noise immunity on longer bus lengths.

It achieves this interface without any restrictions on the normal I

speed. The IC adds minimal loading to the I

remote I

on the number of I

are virtually eliminated. Transmitting SDA and SCL signals via balanced transmission

lines (twisted pairs) or with galvanic isolation (opto-coupling) is simple because separate

directional Tx and Rx signals are provided. The Tx and Rx signals may be directly

connected, without causing latching, to provide an alternative bidirectional signal line with

C-bus logic signals to similar buses having different voltage and current levels.

C-bus properties.

P82B96

Dual bidirectional bus buffer

Rev. 08 — 10 November 2009

Bidirectional data transfer of I

Isolates capacitance allowing 400 pF on Sx/Sy side and 4000 pF on Tx/Ty side

Tx/Ty outputs have 60 mA sink capability for driving low-impedance or high capacitive

buses

400 kHz operation over at least 20 meters of wire (see AN10148 )

Supply voltage range of 2 V to 15 V with I

independent of supply voltage

Splits I

with opto-electrical isolators and similar devices that need unidirectional input and

output signal paths.

Low power supply current

ESD protection exceeds 3500 V HBM per JESD22-A114, 250 V DIP package, 400 V

SO package MM per JESD22-A115, and 1000 V CDM per JESD22-C101

Latch-up free (bipolar process with no latching structures)

Packages offered: DIP8, SO8 and TSSOP8

C-bus nodes are not transmitted or transformed to the local node. Restrictions

C-bus signal into pairs of forward/reverse Tx/Rx, Ty/Ry signals for interface

C-bus devices in a system, or the physical separation between them,

C-bus and a range of other bus conﬁgurations. It can interface

C-bus signals

C-bus node, and loadings of the new bus or

C-bus logic levels on Sx/Sy side

C-bus protocols or clock

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