ADUC847BCP8-5 AD [Analog Devices], ADUC847BCP8-5 Datasheet - Page 46

• Manufacturer Part Number: ADUC847BCP8-5
• Description: MicroConverter Multichannel 24-/16-Bit ADCs with Embedded 62 kB Flash and Single-Cycle MCU
• Manufacturer: AD [Analog Devices]

ADuC845/ADuC847/ADuC848
SF (ADC SINC FILTER CONTROL REGISTER)
The SF register is used to configure the decimation factor for the ADC, and therefore, has a direct influence on the ADC throughput rate.
SFR Address:
Power-On Default:
Bit Addressable:
Table 28. Sinc Filter SFR Bit Designations
SF.7
0
The bits in this register set the decimation factor of the ADC. This has a direct bearing on the throughput rate of the ADC along with the
chop setting. The equations used to determine the ADC throughput rate are
Fadc (Chop On) =
where SFword is in decimal.
Fadc (Chop Off) =
where SFword is in decimal.
Table 29. SF SFR Bit Examples
Chop Enabled (ADCMODE.3 = 0)
SF (Decimal)
13
69
82
255
Chop Disabled (ADCMODE.3 = 1)
SF (Decimal)
3
69
82
255
1
During ADC calibration, the user-programmed value of SF word is used. The SF word does not default to the maximum setting (255) as it
did on previous MicroConverter® products. However, for optimum calibration results, it is recommended that the maximum SF word be set.
With chop enabled, if an SF word smaller than 13 is written to this SF register, the filter automatically defaults to 13.
1
SF (Hexadecimal)
0D
45
52
FF
SF (Hexadecimal)
03
45
52
FF
SF.6
1
3
8
× 8
×
SFword
D4H
45H
No
×
1
SFword
1
× 32.768 kHz
× 32.768 kHz
SF.5
0
Fadc (Hz)
105.3
19.79
16.65
5.35
Fadc (Hz)
1365.3
59.36
49.95
16.06
Tadc (ms)
9.52
50.53
60.06
Tadc (ms)
0.73
16.84
20.02
186.77
62.25
SF.4
0
Rev. A | Page 46 of 108
Tsettle (ms)
19.04
101.1
120.1
373.54
Tsettle (ms)
2.2
50.52
60.06
186.8
SF.3
0
SF.2
1
0
SF.1
SF.0
1