ADUC847BCP8-5 AD [Analog Devices], ADUC847BCP8-5 Datasheet - Page 27

• Manufacturer Part Number: ADUC847BCP8-5
• Description: MicroConverter Multichannel 24-/16-Bit ADCs with Embedded 62 kB Flash and Single-Cycle MCU
• Manufacturer: AD [Analog Devices]

Signal Chain Overview (Chop Enabled, CHOP = 0)
With the CHOP bit = 0 (see the ADCMODE SFR bit designa-
tions in Table 24), the chopping scheme is enabled. This is the
default condition and gives optimum performance in terms of
offset errors and drift performance. With chop enabled, the
available output rates vary from 5.35 Hz to 105 Hz (SF = 255
and 13, respectively). A typical block diagram of the ADC input
channel with chop enabled is shown in Figure 12.
The sampling frequency of the modulator loop is many times
higher than the bandwidth of the input signal. The integrator in
the modulator shapes the quantization noise (which results
from the analog-to-digital conversion) so that the noise is pushed
toward one-half of the modulator frequency. The output of the
Σ-Δ modulator feeds directly into the digital filter. The digital
filter then band-limits the response to a frequency significantly
lower than one-half of the modulator frequency. In this manner,
the 1-bit output of the comparator is translated into a band
limited, low noise output from the ADCs.
The ADC filter is a low-pass Sinc
primary function is to remove the quantization noise introduced
at the modulator. The cutoff frequency and decimated output
data rate of the filter are programmable via the Sinc filter word
loaded into the filter (SF) register (see Table 28). The complete
signal chain is chopped, resulting in excellent dc offset and
offset drift specifications and is extremely beneficial in applica-
tions where drift, noise rejection, and optimum EMI rejection
are important.
ANALOG
INPUT
F
MUX
CHOP
3
or (sinx/x)
BUF
Figure 12. Block Diagram of the ADC Input Channel with Chop Enabled
3
PGA
filter whose
F
IN
F
MOD
MOD
Σ-∆
Rev. A | Page 27 of 108
F
XOR
CHOP
With chop enabled, the ADC repeatedly reverses its inputs. The
decimated digital output words from the Sinc
have a positive offset and a negative offset term included. As a
result, a final summing stage is included so that each output
word from the filter is summed and averaged with the previous
filter output to produce a new valid output result to be written
to the ADC data register. Programming the Sinc
factor is restricted to an 8-bit register called SF (see Table 28),
the actual decimation factor is the register value times 8.
Therefore, the decimated output rate from the Sinc
the ADC conversion rate) is
where:
f
SF is the decimal equivalent of the word loaded to the filter
register.
f
The chop rate of the channel is half the output data rate:
As shown in the block diagram (Figure 12), the Sinc
outputs alternately contain +V
respective channel offset.
SINC
ADC
MOD
is the ADC conversion rate.
3
is the modulator sampling rate of 32.768 kHz.
FILTER
f
f
CHOP
ADC
=
=
1
3
2
×
×
3 × (8 × SF)
8
f
×
1
ADC
1
SF
ADuC845/ADuC847/ADuC848
AIN + V
AIN – V
×
F
f
ADC
MOD
OS
OS
OS
Σ-∆
2
and −V
DIGITAL
OUTPUT
OS
, where V
3
filter, therefore,
3
decimation
3
OS
3
filter (and
filter
is the