ADUC847BCP8-5 AD [Analog Devices], ADUC847BCP8-5 Datasheet - Page 28

• Manufacturer Part Number: ADUC847BCP8-5
• Description: MicroConverter Multichannel 24-/16-Bit ADCs with Embedded 62 kB Flash and Single-Cycle MCU
• Manufacturer: AD [Analog Devices]

ADuC845/ADuC847/ADuC848
This offset is removed by performing a running average of 2.
This average by 2 means that the settling time to any change in
programming of the ADC is twice the normal conversion time,
while an asynchronous step change on the analog input is not
fully reflected until the third subsequent output. See Figure 13.
t
SETTLE
=
f
ADC
2
=
2
×
t
ADC
SAMPLE 1
SAMPLE 1
NO/INVALID
NO OUTPUT
OUTPUT
Figure 14. ADC Settling Time Following an Asynchronous Change with
Figure 13. ADC Settling Time Following a Synchronous Change with
SAMPLE 2
SAMPLE 2
SAMPLE 1 + SAMPLE 2
SAMPLE 1 + SAMPLE 2
VALID OUTPUT
VALID OUTPUT
2
2
SYNCHRONOUS CHANGE
SAMPLE 3
SAMPLE 3
(I.E. CHANNEL CHANGE)
SAMPLE 2 + SAMPLE 3
(I.E. DISCONTINUOUS INPUT CHANGE)
SAMPLE 2 + SAMPLE 3
VALID OUTPUT
VALID OUTPUT
ASYNCHRONOUS CHANGE
Rev. A | Page 28 of 108
2
2
Chop Enabled
Chop Enabled
SAMPLE 4
SAMPLE 4
SAMPLE 3 + SAMPLE 4
SAMPLE 3 + SAMPLE 4
UNSETTLED OUTPUT
NO OUTPUT
2
2
SAMPLE 5
SAMPLE 5
SAMPLE 4 + SAMPLE 5
SAMPLE 4 + SAMPLE 5
The allowable range for SF (chop enabled) is 13 to 255 with
a default of 69 (45H). The corresponding conversion rates,
rms and peak-to-peak noise performances are shown in
Table 10, Table 11, Table 12, and Table 13. The numbers are
typical and generated at a differential input voltage of 0 V
and a common-mode voltage of 2.5 V. Note that the con-
version time increases by 0.732 ms for each increment in SF.
UNSETTLED OUTPUT
VALID OUTPUT
2
2
SAMPLE 6
SAMPLE 6
SAMPLE 5 + SAMPLE 6
SAMPLE 5 + SAMPLE 6
VALID OUTPUT
VALID OUTPUT
2
2