DS567 XILINX [Xilinx, Inc], DS567 Datasheet - Page 3

• Manufacturer Part Number: DS567
• Description: DDR2 Memory Controller for PowerPC 440 Processors
• Manufacturer: XILINX [Xilinx, Inc]

DS567 (v1.1.1) March 31, 2008
Table 1: PPC440MC DDR2 Memory Controller I/O Signal Description (Cont’d)
MIMCROWCONFLICT
MCMIREADDATA[0:127]
MCMIREADDATAVALID
MCMIREADDATAERR
MCMIADDRREADYTOACCEPT
DDR2_DQ
(C_DDR_DWIDTH – 1:0)
DDR2_DQS
(C_DDR_DQS_WIDTH – 1:0)
DDR2_DQS_N
(C_DDR_DQS_WIDTH – 1:0)
DDR2_A
(C_DDR_CAWIDTH – 1:0)
DDR2_BA
(C_DDR_BAWIDTH – 1:0)
DDR2_RAS_N
DDR2_CAS_N
DDR2_WE_N
DDR2_CS_N
(C_NUM_RANKS_MEM – 1 down to 0)
DDR2_ODT
(C_DDR2_ODT_WIDTH – 1:0)
DDR2_CKE
(C_DDR2_NUM_RANKS_MEM – 1:0)
DDR2_DM
(C_DDR_DM_WIDTH – 1:0)
DDR2_CK
(C_NUM_CLK_PAIRS – 1:0)
DDR2_CK_N
(C_NUM_CLK_PAIRS – 1:0)
MI_MCCLK
MI_MCCLK90
MI_MCCLKDIV2
MI_MCCLK_200
MI_MCRST
Signal Name
System Clock and Reset Signals
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Interface
DDR2
DDR2
DDR2
DDR2
DDR2
DDR2
DDR2
DDR2
DDR2
DDR2
DDR2
DDR2
DDR2
DDR2
CLK
CLK
CLK
CLK
RST
MCI
MCI
MCI
MCI
MCI
DDR2 Memory Controller for PowerPC 440 Processors
DDR2 Signals
Signal
Type
I/O
I/O
I/O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
Status
Initial
This signal is asserted if the row being
accessed is different from the row
accessed in the previous command
Read data bus
When asserted, this signal indicates the
data on the read data bus is valid
This signal is asserted when an
uncorrectable error is detected by the
ECC logic.
This signal is asserted when the
PPC440MC DDR2 Memory Controller is
ready to accept transactions
DDR2 data bus
DDR2 data strobe
DDR2 inverted data strobe
DDR2 address
DDR2 bank address
DDR2 row address strobe
DDR2 column address strobe
DDR2 write enable
DDR2 chip selects
DDR2 ODT enable signal
DDR2 clock enable signal
DDR2 data mask
DDR2 clock
DDR2 inverted clock
Clock
Clock phase shifted by 90
Clock divided by 2
IDELAY reference clock
Reset
Description
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