DS567 XILINX [Xilinx, Inc], DS567 Datasheet - Page 19

• Manufacturer Part Number: DS567
• Description: DDR2 Memory Controller for PowerPC 440 Processors
• Manufacturer: XILINX [Xilinx, Inc]

DS567 (v1.1.1) March 31, 2008
Bank Management
The PPC440MC DDR2 Memory Controller can keep four banks open. The banks are opened as
commands are processed by the PPC440MC DDR2 Memory Controller. When four banks are already
opened and a command occurs for a different bank, the least recently used bank is closed and the new
bank is opened. All the banks are closed during auto refresh. After the auto refresh, the PPC440MC
DDR2 Memory Controller opens the bank last accessed before the auto refresh command. The conflict
logic in the MCI always compares the current address to the previous address to determine the bank
and row conflicts. There are no signals from the PPC440MC DDR2 Memory Controller to the MCI,
indicating that all the banks are closed during the auto refresh. The MCI does not assert the conflict bit
for the first command that it presents after auto refresh, if the banks and row address of that command
is the same as the command that was last presented before the auto refresh. To avoid missing the
conflict, the PPC440MC DDR2 Memory Controller, after the auto refresh command, opens the last
accessed bank and row. The flow diagram in
X-Ref Target - Figure 11
The PPC440MC DDR2 Memory Controller has four internal bank registers. The width of the internal
bank registers depends on the row and bank address widths. The internal bank registers hold bank
information, row information, and a status bit. The status bit holds the open and close status of the bank
and row in the internal bank register. If the status bit is set, the bank and row in the internal register are
opened; otherwise the contents of the internal register does not hold any significance. The status bit is
cleared during the assertion of reset and auto refresh because the banks and row are closed during that
time. The internal bank register contents are updated as bank and rows are opened.
Update LRU Table
Figure 11: Bank Management Flow Diagram
N
N
Y
Bank Hit and a Row Miss?
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Command with Conflict
Activate Bank and Row
Four Banks Open?
Close LRU Bank
Conflict Fake?
DDR2 Memory Controller for PowerPC 440 Processors
Figure 11
N
N
Y
Y
shows the bank management flow.
Y
Close Current Bank
and Row
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