DS567 XILINX [Xilinx, Inc], DS567 Datasheet
DS567
Related parts for DS567
DS567 Summary of contents
Page 1
... Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, and other designated brands included herein are trademarks of Xilinx, Inc. PowerPC is a trademark of IBM Corp. and used under license. All other trademarks are the property of their respective owners. DS567 (v1.1.1) March 31, 2008 DDR2 Memory Controller for ...
Page 2
... Data bus Byte enable for the data on the data bus When asserted, this signal indicates the data on the data bus is valid This signal is asserted if the bank being accessed is different from the bank accessed in the previous command DS567 (v1.1.1) March 31, 2008 ...
Page 3
... DDR2_DM (C_DDR_DM_WIDTH – 1:0) DDR2_CK (C_NUM_CLK_PAIRS – 1:0) DDR2_CK_N (C_NUM_CLK_PAIRS – 1:0) MI_MCCLK MI_MCCLK90 MI_MCCLKDIV2 MI_MCCLK_200 MI_MCRST DS567 (v1.1.1) March 31, 2008 DDR2 Memory Controller for PowerPC 440 Processors Signal Initial Interface Type Status MCI I This signal is asserted if the row being accessed is different from the row ...
Page 4
... All supported memory column 10 address widths Unbuffered memory Registered memory 0 = Disables ODT ODT enabled 75Ω ODT enabled 150Ω ODT enabled 50Ω 15000 DS567 (v1.1.1) March 31, 2008 ...
Page 5
... UCF. The location coordinates for the IDELAYCTRL primitive depend on the FPGA bank being used and can be determined using FPGA editor. The optimal UCFs provided in the pcore directory already have the location constraints for the IDELAYCTRL primitives. DS567 (v1.1.1) March 31, 2008 DDR2 Memory Controller for PowerPC 440 Processors Parameter Name ...
Page 6
... C_DQ_IO_MS DS567 (v1.1.1) March 31, 2008 ...
Page 7
... Memory Rank 1 Base Address = 0x1000_0000 Memory Rank 1 High Address = 0x1FFF_FFFF Memory Rank 2 Base Address = 0x2000_0000 Memory Rank 2 High Address = 0x2FFF_FFFF Memory Rank 3 Base Address = 0x3000_0000 Memory Rank 3 High Address = 0x3FFF_FFFF DS567 (v1.1.1) March 31, 2008 DDR2 Memory Controller for PowerPC 440 Processors C_DQS_IO_COL 0b000000000000000000 0b1010110101010110101010101010101011 010101010110101010101011010101010110 10 ...
Page 8
... Parameter affects size of DDR DM signals. Affects size of signal. Affects size of signal. Size depends on C_NUM_CLK_PAIRS parameter. C_NUM_RANKS_MEM parameter. Size depends on parameter setting. Size depends on parameter setting. Size depends on parameter setting. Size depends on parameter setting. Size depends on parameter setting. DS567 (v1.1.1) March 31, 2008 ...
Page 9
... MIMCADDRESS [(C_DDR_RAWIDTH + C_DDR_CAWIDTH + Address Offset – Row Address (C_DDR_CAWIDTH + Address Offset)] MIMCADDRESS [(C_DDR_BAWIDTH + C_DDR_RAWIDTH + C_DDR_CAWIDTH + Bank Address Address Offset – (C_DDR_RAWIDTH + C_DDR_CAWIDTH + Address Offset)] DS567 (v1.1.1) March 31, 2008 DDR2 Memory Controller for PowerPC 440 Processors Table 5 PPC440MC DDR2 to DDR2 Signal DDR2_DQ[C_DDR_DWIDTH – 1:0] DDR2_A[C_DDR_AWIDTH – 1:0] DDR2_BA[C_DDR_BAWIDTH – ...
Page 10
... MCI_ADDR_WIDTH – (C_DDR_CAWIDTH+ADDR_OFFSET) 32 – COLADDR_STARTBIT + C_DDR_CAWIDTH – 1 COLADDR_STARTBIT – C_DDR_AWIDTH ROWADDR_STARTBIT + C_DDR_AWIDTH – 1 ROWADDR_STARTBIT – C_DDR_BAWIDTH BANKADDR_STARTBIT + C_DDR_BAWIDTH – 1 (C_DDR_DWIDTH/8). 2 (64/ www.xilinx.com Equation Value log (32/ – – – DS567 (v1.1.1) March 31, 2008 Table 7 ...
Page 11
... Column Address Width = 10 • Row Address Width = 14 • Bank Address Width = 3 The MI_ROWCONFLICT_MASK and MI_BANKCONFLICT_MASK parameters are: • MI_ROWCONFLICT_MASK = 32'h003fff00 • MI_BANKCONFLICT_MASK = 32'h01c00000 DS567 (v1.1.1) March 31, 2008 DDR2 Memory Controller for PowerPC 440 Processors ... 2223 14-bit Row Address ... 8 9 2223 ...
Page 12
... X-Ref Target - Figure 4 Write Data Rise Write Data Fall FPGA Clock 12 Figure 3. DDR2 SDRAM MC_TOP Clock, Reset, I/O Control Figure 4, is implemented using the IOB ODDR in the same edge mode Figure 4: Write Datapath www.xilinx.com MCI DS567_03_030608 DQ ODDR ds567_04_022708 DS567 (v1.1.1) March 31, 2008 ...
Page 13
... DQS strobe being 3-stated by the memory from clocking the IDDR flip-flop. There is one such circuit per DQS group. The read datapath is shown in X-Ref Target - Figure 5 DQ IDELAY BUFIO DQS IDELAY DQS Gate DS567 (v1.1.1) March 31, 2008 DDR2 Memory Controller for PowerPC 440 Processors Figure 5. IOB CLB IDDR ...
Page 14
... FIFOs. 14 Figure 6) powers up and initializes the DDR2 device and Idle EMR2 EMR3 LM1 LM2 Figure 6: Initialization State Machine Flow "Interfacing to the MCI." www.xilinx.com Calib done Calib_read2 Calib_write2 Calib_read1 Calib_write1 Activate 200 Cycle Wait LM3 DS567_07_071607 DS567 (v1.1.1) March 31, 2008 ...
Page 15
... MCI for up to two clocks after the deassertion of the MCMIADDRREADYTOACCEPT signal. The transaction that was accepted by the PPC440MC DDR2 Memory Controller after the deassertion of the MCMIADDRREADYTOACCEPT signal is processed after the auto refresh command completes. DS567 (v1.1.1) March 31, 2008 DDR2 Memory Controller for PowerPC 440 Processors www.xilinx.com 15 ...
Page 16
... Figure 8: Write Command During Auto Refresh and MCMIADDRREADYTOACCEPT Deasserted 16 14, the DDR2 burst size Wr,A0 Wr,A1 auto refresh command Wr,A0 Auto,ref www.xilinx.com auto_ref A0,D0 A0,D2 A1,D0 A1,D2 A0,D1 A0,D3 A1,D1 A1,D3 DS567_08_071607 completes. The assertion Wr,A1 DS567_09_071607 DS567 (v1.1.1) March 31, 2008 the ...
Page 17
... The PPC440MC DDR2 Memory Controller evaluates this conflict as a fake conflict and does not deassert the MCMIADDRREADYTOACCEPT signal. The PPC440MC DDR2 Memory Controller takes one clock to evaluate the conflict, and there are at least four idle cycles in the DDR2_data_bus. DS567 (v1.1.1) March 31, 2008 DDR2 Memory Controller for PowerPC 440 Processors the PPC440MC ...
Page 18
... At the end of the initialization and calibration sequence, the PPC440MC DDR2 Memory Controller asserts the MCMIADDRREADYTOACCEPT signal. The calibration sequence is done once during initialization and is not repeated B0,R0 B1,R1 Wr,B0 www.xilinx.com B0,R0 Rd,B1 Wr,B0 DS567_11_071607 DS567 (v1.1.1) March 31, 2008 17 18 ...
Page 19
... The internal bank register contents are updated as bank and rows are opened. DS567 (v1.1.1) March 31, 2008 DDR2 Memory Controller for PowerPC 440 Processors Figure 11 shows the bank management flow ...
Page 20
... X-Ref Target - Figure 12 mi_mc_clk MIMCBANKCONFLICT/ MIMCROWCONFLICT MIMCADDRESSVALID MIMCADDRESS MIMCREADNOTWRITE MCMIADDRREADYTOACCEPT internal_auto_ref_flag cmd_to_DDR2 internal_conflict internal_bank0 internal_bank1 internal_bank2 internal_bank3 Figure 12: Bank Management with No Internal Banks Open B0,R0 Act,B0 Wr,B0 B0,R0 www.xilinx.com 20 40 B1,R1 B3,R0 Act,B1 Wr,B1 B1,R1 B0,R0 DS567_13_071607 DS567 (v1.1.1) March 31, 2008 Act,B3 B2,R0 B1,R1 B0,R0 ...
Page 21
... X-Ref Target - Figure 13 mi_mc_clk MIMCBANKCONFLICT/ MIMCROWCONFLICT MIMCADDRESSVALID MIMCADDRESS MIMCREADNOTWRITE MCMIADDRREADYTOACCEPT internal_auto_ref_flag cmd_to_DDR2 internal_conflict internal_bank0 internal_bank1 internal_bank2 internal_bank3 Figure 13: Bank Management with Four Internal Banks Open DS567 (v1.1.1) March 31, 2008 DDR2 Memory Controller for PowerPC 440 Processors 7. The PPC440MC DDR2 Memory B0,R0 B1,R1 B3,R0 Wr,B0 Wr,B1 ...
Page 22
... MIMCBANKCONFLICT/ MIMCROWCONFLICT MIMCADDRESSVALID MIMCADDRESS MIMCREADNOTWRITE MCMIADDRREADYTOACCEPT internal_auto_ref_flag cmd_to_DDR2 internal_conflict internal_bank0 internal_bank1 internal_bank2 internal_bank3 B7,R0 Act,B7 Wr,B7 B4, R0 B7, R0 B0, R0 B4, R0 B2, R0 B0, R0 B1, R0 B1, R0 Figure 14: Bank Management During Auto Refresh www.xilinx.com 46 50 B7,R0 Pre all Auto re Act,B7 B7, R0 DS567_15_071607 DS567 (v1.1.1) March 31, 2008 ...
Page 23
... The HDL implementation modules automatically instantiate the necessary FPGA OBUF and IOBUF resources for the DDR I/O signals. To analyze the timing within the FPGA, the design has been implemented to illustrate the FPGA performance and resource utilization values as shown in DS567 (v1.1.1) March 31, 2008 DDR2 Memory Controller for PowerPC 440 Processors bit error ...
Page 24
... Release with ISE 10.1 SP1 EDK software release. Minor publication issue. LIMITED TO ANY WARRANTIES www.xilinx.com Device Resources Block Slice 6-input Slices RAM Flip-Flops LUTs 540 3 1105 1019 680 3 1415 1255 900 4 2025 1985 1527 6 2942 2230 OR REPRESENTATIONS THAT THIS DS567 (v1.1.1) March 31, 2008 ...