DS89C420-ENL MAXIM [Maxim Integrated Products], DS89C420-ENL Datasheet - Page 39

• Manufacturer Part Number: DS89C420-ENL
• Description: Ultra-High-Speed Microcontroller
• Manufacturer: MAXIM [Maxim Integrated Products]

When the DS89C420 enters stop mode, the bandgap, reset comparator, and power- fail interrupt
comparator are automatically disabled to conserve power, if the BGS (EXIF.0) bit is set to a logic 0. This
is the lowest power mode. If BGS is set to a logic 1, the bandgap reference, reset comparator, and the
power- fail comparator are powered up, although in a reduced fashion, while in stop mode.
WATCHDOG TIMER
The watchdog timer functions as the source of both the watchdog interrupt and the watchdog reset. When
the clock divider is set to 10b, the interrupt timeout has a default divide ratio of 2
clock, with the watchdog reset set to timeout 512 system clock cycles later. This results in a 33MHz
crystal oscillator producing an interrupt timeout every 3.9718ms, followed 15.5µs later by a watchdog
reset. The watchdog timer is reset to the default divide ratio following any reset. Using the WD0 and
WD1 bits in the clock control (CKCON.6 and 7) register, other divide ratios can be selected for longer
watchdog interrupt periods. Table 14 summarizes the watchdog bit settings and the timeout values.
Note: All watchdog-timer reset timeouts follow the programmed interrupt timeouts by 512 system clock
cycles, which equates to varying numbers of oscillator cycles depending on the clock-divide (CD1:0) and
crystal multiplier settings.
Table 14. WATCHDOG TIMEOUT VALUE (IN NUMBER OF OSCILLATOR
CLOCKS)
4X
A watchdog control (WDCON) SFR is used for programming the functions. EWT (WDCON.1) is the
enable for the watchdog-timer reset function and RWT (WDCON.0) is the bit used to restart the
watchdog timer. Setting the RWT bit restarts the timer for another full interval. If the watchdog timer
reset function is masked by the EWT bit and no resets are issued to the timer through the RWT bit, the
watchdog timer generates interrupt timeouts at a rate determined by the programmed divide ratio. WDIF
(WDCON.3) is the interrupt flag set at timer termination and WTRF (WDCON.2) is the reset flag set
following a watchdog reset timeout. The watchdog interrupt is enabled by the EWDI bit (EIE.4) when it
is set to 1. The watchdog timer reset and interrupt timeouts are measured by counting system clock
cycles.
An independent watchdog timer functions as the crystal startup counter to count 65,536 crystal clock
cycles before allowing the crystal oscillator to function as the system clock. This warmup time is verified
by the watchdog timer following each power-up as well as each time the crystal is restarted following a
stop mode. The watchdog is also used to establish a startup time whenever the CTM in the PMR register
is set to enable the crystal multiplier (4X/
One of the applications of the watchdog timer is for the watchdog to wake up the system from idle mode.
The watchdog interrupt can be programmed to allow a system to wake up periodically to sample the
external world.
/
1
0
x
x
x
2
X
CD1:0
00
00
01
10
11
WATCHDOG INTERRUPT TIMEOUT
WD1:0 = 00
2
2
2
2
2
15
16
17
17
27
WD1:0 = 01 WD1:0 = 10 WD1:0 = 11
2
2
2
2
2
18
19
20
20
30
2
2
2
2
2
21
22
23
23
33
2
X
).
39 of 58
2
2
2
2
2
24
25
26
26
36
2
WD1:0 = 00
2
2
2
2
27
15
16
17
17
+ 524,288
+ 128
+ 256
+ 512
+ 512
WATCHDOG RESET TIMEOUT
2
WD1:0 = 01
2
2
2
2
30
18
19
20
20
+ 524,288
+ 128
+ 256
+ 512
+ 512
17
2
of the crystal oscillator
WD1:0 = 10
2
2
2
2
33
21
22
23
23
+ 524,288
+ 128
+ 256
+ 512
+ 512
2
WD1:0 = 11
2
2
2
2
36
DS89C420
24
25
26
26
+ 524,288
+ 128
+ 256
+ 512
+ 512