DS89C420-ENL MAXIM [Maxim Integrated Products], DS89C420-ENL Datasheet - Page 38

• Manufacturer Part Number: DS89C420-ENL
• Description: Ultra-High-Speed Microcontroller
• Manufacturer: MAXIM [Maxim Integrated Products]

the multiplier startup counter. During the multiplier startup period the CKRY bit remains cleared and the
CD1 and CD0 clock controls cannot be set to 00b. The CTM bit is cleared to a logic 0 on all resets.
Figure 10 gives a simplified diagram of the generation of the system clocks. Specifics of hardware
restrictions associated with the use of the 4X/
SFR description.
Figure 10. SYSTEM CLOCK SOURCES
BANDGAP-MONITORED INTERRUPT AND RESET GENERATION
The power monitor in the DS89C420 monitors the V
reference. Whenever V
interrupt-enable bit EPFI (WDCON.5) is set, causing the device to vector to address 33h. The power- fail
interrupt-status bit PFI (WDCON.4) is set anytime V
by software once set. Similarly, as V
execution. Following power- up, a power-on reset initiates a power-on reset timeout before starting
program execution. When V
V
and the clock source has had time to stabilize. Once the reset timeout period has elapsed, the reset
condition is removed automatically and software execution begins at the reset vector location of 0000h.
The power-on reset flag POR (WDCON.6) is set to logic 1 to indicate a power-on reset has occurred, and
can only be cleared by software.
CC
> V
RST
Oscillator
Crystal
and a delay of 65,536 oscillator cycles has elapsed, to ensure that power is within tolerance
CC
falls below V
Ring
Enable
CC
4X/2X
CTM
is first applied to the DS89C420, the processor is held in reset until
CC
PFW
falls below V
Divide 1024
, an interrupt is generated if the corresponding power- fail
Multiplier
Oscillator
2
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Clock
X
Ring
CTM, CKRY, CD1, and CD0 bits are outlined in the
CC
CC
RST
transitions below V
CD0
CD1
pin in relation to the on-chip bandgap voltage
, a reset is issued internally to halt program
Selector
MUX
PFW
, and can only be cleared
System
Clock
DS89C420