DZPD6722VCCE INTEL [Intel Corporation], DZPD6722VCCE Datasheet - Page 72

• Manufacturer Part Number: DZPD6722VCCE
• Description: ISA-to-PC-Card (PCMCIA) Controllers
• Manufacturer: INTEL [Intel Corporation]

PD6710/’22 — ISA-to-PC-Card (PCMCIA) Controllers
10.2
a.
10.3
72
Register Name: FIFO Control
Index: 17h
Register Name: Misc Control 2
Index: 1Eh
1. Because a write will flush the FIFO, these scratchpad bits should be used only when card activity is guaranteed not to occur.
Empty Write
IRQ15 Is RI
RW:0
FIFO
Bit 7
Bit 7
RW
Out
DMA System
FIFO Control
Bit 7 — Empty Write FIFO
This bit controls FIFO operation and reports FIFO status. When this bit is written to ‘1’, all data in
the FIFO is lost. During read operations when this bit is ‘1’, the FIFO is empty. During read
operations when this bit is ‘0’, data is still in the FIFO. This bit is used to ensure the FIFO is empty
before changing timing registers.
FIFO contents will be lost whenever any of the following occur:
Misc Control 2
(PD6722)
•
•
•
RW:0
Bit 6
Bit 6
Value
PWRGOOD pin (
The card is removed.
V
0
1
CC
Power bit (see
I/O Read
FIFO not empty
FIFO empty
Three-State
RW:0
Bit 5
Bit 5
Bit 7
Table
“Bit 4 — VCC Power” on page
1) is ‘0’.
Drive LED
Enable
RW:0
Bit 4
Bit 4
Scratchpad Bits
RW:0000000
5V Core
RW:0
Bit 3
Bit 3
a
50) is programmed to ‘0’.
I/O Write
No operation occurs; default on reset
Flush the FIFO
Suspend
RW:0
Bit 2
Bit 2
Register Compatibility Type: ext.
Register Compatibility Type: ext.
Low-Power
Dynamic
Mode
RW:1
Bit 1
Bit 1
Register Per: socket
Register Per: chip
Synthesizer
Frequency
Datasheet
Bypass
RW:0
Bit 0
Bit 0