DZPD6722VCCE INTEL [Intel Corporation], DZPD6722VCCE Datasheet - Page 66
DZPD6722VCCE
Manufacturer Part Number
DZPD6722VCCE
Description
ISA-to-PC-Card (PCMCIA) Controllers
Manufacturer
INTEL [Intel Corporation]
Datasheet
1.DZPD6722VCCE.pdf
(138 pages)
- Current page: 66 of 138
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PD6710/’22 — ISA-to-PC-Card (PCMCIA) Controllers
9.3
9.4
66
Register Name: System Memory Map 0–4 End Address Low
Index: 12h, 1Ah, 22h, 2Ah, 32h
Register Name: System Memory Map 0–4 End Address High
Index: 13h, 1Bh, 23h, 2Bh, 33h
Bit 7
Bit 7
Card Timer Select
RW:00
System Memory Map 0–4 End Address Low
There are five separate System Memory Map End Address Low registers, each with identical
fields. These registers are located at the following indexes:
Bits 7:0 — End Address 19:12
This register contains the least-significant byte of the address that specifies where in the memory
space the corresponding memory map will end. Memory accesses that are equal or below this
address and equal or above the corresponding System Memory Map Start Address will be mapped
into the memory space of the corresponding PC Card.
The most-significant four bits are located in the System Memory Map 0–4 End Address High
register (see
System Memory Map 0–4 End Address High
There are five separate System Memory Map End Address High registers, each with identical
fields. These registers are located at the following indexes:
Bit 6
Bit 6
Index
12h
1Ah
22h
2Ah
32h
Index
13h
1Bh
“System Memory Map 0–4 End Address High” on page
Bit 5
Bit 5
System Memory Map End Address Low
System Memory Map 0 End Address Low
System Memory Map 1 End Address Low
System Memory Map 2 End Address Low
System Memory Map 3 End Address Low
System Memory Map 4 End Address Low
System Memory Map End Address High
System Memory Map 0 End Address High
System Memory Map 1 End Address High
Scratchpad Bits
RW:00
Bit 4
Bit 4
End Address 19:12
RW:00000000
Bit 3
Bit 3
Bit 2
Bit 2
End Address 23:20
RW:0000
Register Compatibility Type: 365
66).
Register Compatibility Type: 365
Bit 1
Bit 1
Register Per: socket
Register Per: socket
Datasheet
Bit 0
Bit 0
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