DZPD6722VCCE INTEL [Intel Corporation], DZPD6722VCCE Datasheet - Page 60
DZPD6722VCCE
Manufacturer Part Number
DZPD6722VCCE
Description
ISA-to-PC-Card (PCMCIA) Controllers
Manufacturer
INTEL [Intel Corporation]
Datasheet
1.DZPD6722VCCE.pdf
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PD6710/’22 — ISA-to-PC-Card (PCMCIA) Controllers
8.3
8.4
60
Register Name: System I/O Map 0–1 Start Address High
Index: 09h, 0Dh
Register Name: System I/O Map 0–1 End Address Low
Index: 0Ah, 0Eh
Bit 7
Bit 7
Bits 7:0 — Start Address 7:0
This register contains the least-significant byte of the address that specifies the beginning of the I/O
space within the corresponding I/O map. I/O accesses that are equal or above this address and equal
or below the corresponding System I/O Map End Address will be mapped into the I/O space of the
corresponding PC Card.
The most-significant byte is located in the System I/O Map 0–1 Start Address High register (see
“System I/O Map 0–1 Start Address High” on page
System I/O Map 0–1 Start Address High
There are two separate System I/O Map Start Address High registers, each with
identical fields. These registers are located at the following indexes:
Bits 15:8 — Start Address 15:8
This register contains the most-significant byte of the Start Address. See the description of the Start
Address field associated with bits 7:0 of the System I/O Map 0–1 Start Address Low register.
System I/O Map 0–1 End Address Low
There are two separate System I/O Map End Address Low registers, each with identical fields.
These registers are located at the following indexes:
Bit 6
Bit 6
Index
9h
Dh
Bit 5
Bit 5
System I/O Map Start Address High
System I/O Map 0 Start Address High
System I/O Map 1 Start Address High
Bit 4
Bit 4
Start Address 15:8
End Address 7:0
RW:00000000
RW:00000000
Bit 3
Bit 3
60).
Bit 2
Bit 2
Register Compatibility Type: 365
Register Compatibility Type: 365
Bit 1
Bit 1
Register Per: socket
Register Per: socket
Datasheet
Bit 0
Bit 0
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