DZPD6722VCCE INTEL [Intel Corporation], DZPD6722VCCE Datasheet - Page 116
DZPD6722VCCE
Manufacturer Part Number
DZPD6722VCCE
Description
ISA-to-PC-Card (PCMCIA) Controllers
Manufacturer
INTEL [Intel Corporation]
Datasheet
1.DZPD6722VCCE.pdf
(138 pages)
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PD6710/’22 — ISA-to-PC-Card (PCMCIA) Controllers
116
1. The Setup time is determined by the value programmed into the Setup Timing register, index 3Ah/3Dh. Using the Timer Set
2. The Command time is determined by the value programmed into the Command Timing register, index 3Bh/3Eh. Using the
3. The Recovery time is determined by the value programmed into the Recovery Timing register, index 3Ch/3Fh. Using the
4. Based on an internal clock period of 40 ns (25 MHz).
Symbol
-IOWR, -IORD
0 default value of 01h, the setup time would be 70 ns. S = (N
page
Timer Set 0 default value of 06h, the Command time would be 270 ns. C = (N
Timer Set 0 default value of 03h, the hold (Recovery) time would be 150 ns. R = (N
Figure 27. 16-Bit System to 8-Bit I/O Card: Odd Byte Timing
Table 36. DMA Read Cycle Timing (PD6722 only) (Sheet 1 of 2)
Read Cycle
Write Cycle
Write Cycle
t
t
t
t
t
t
1
2
3
4
5
6
Read or
109.
-IOIS16
A[25:0]
D[15:8]
D[7:0]
-REG,
D[7:0]
-CE2
-CE1
DRQ (IRQ10) and DACK* (IRQ9) active to DMA cycle begin
-CE[2:1], -REG, -IORD, -OE, and Write Data setup to -IOWR
active
Command: -IOWR pulse width
Recovery: -IOWR inactive to end of cycle
-WAIT active from -IOWR active
-WAIT inactive to -IOWR inactive
1
t
1
t
4
Parameter
t
t
2
2
3
3
Odd Data
XX
pres
t
5
N
val
+ 1), see
Odd Data
(S
(C
(R
pres
“PC Card Bus Timing Calculations” on
2 Tcp
Tcp) – 10
Tcp) – 10
Tcp) – 10
MIN
40
pres
N
val
+ 1), see page 109.
N
val
+ 1), see page 109.
(C – 2)Tcp – 10
t
6
MAX
Datasheet
Units
ns
ns
ns
ns
ns
ns
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