DZPD6722VCCE INTEL [Intel Corporation], DZPD6722VCCE Datasheet - Page 62
DZPD6722VCCE
Manufacturer Part Number
DZPD6722VCCE
Description
ISA-to-PC-Card (PCMCIA) Controllers
Manufacturer
INTEL [Intel Corporation]
Datasheet
1.DZPD6722VCCE.pdf
(138 pages)
- Current page: 62 of 138
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PD6710/’22 — ISA-to-PC-Card (PCMCIA) Controllers
8.6
8.7
62
Register Name: Card I/O Map 0–1 Offset Address Low
Index: 36h, 38h
Register Name: Card I/O Map 0–1 Offset Address High
Index: 37h, 39h
1. This bit must be programmed to ‘0’.
Bit 7
Bit 7
Card I/O Map 0–1 Offset Address Low
There are two separate Card I/O Map Offset Address Low registers, each with identical fields.
These registers are located at the following indexes:
Bits 7:1 — Offset Address 7:1
This register contains the least-significant byte of the quantity that will be added to the host I/O
address; this will determine the PC Card I/O map location where the I/O access will occur.
The most-significant byte is located in the Card I/O Map 0–1 Offset Address High register (see
“Card I/O Map 0–1 Offset Address High” on page
Card I/O Map 0–1 Offset Address High
There are two separate Card I/O Map Offset Address High registers, each with identical fields.
These registers are located at the following indexes:
Bit 6
Bit 6
Index
36h
38h
Index
37h
39h
Bit 5
Bit 5
Card I/O Map Offset Address Low
Card I/O Map 0 Offset Address Low
Card I/O Map 1 Offset Address Low
Card I/O Map Offset Address High
Card I/O Map 0 Offset Address High
Card I/O Map 1 Offset Address High
Offset Address 7:1
RW:0000000
Bit 4
Bit 4
Offset Address 15:8
RW:00000000
Bit 3
Bit 3
62).
Bit 2
Bit 2
Register Compatibility Type: ext.
Register Compatibility Type: ext.
Bit 1
Bit 1
Register Per: socket
Register Per: socket
Datasheet
RW:0
Bit 0
Bit 0
0
1
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