MC68HC908GR4 MOTOROLA [Motorola, Inc], MC68HC908GR4 Datasheet - Page 136
MC68HC908GR4
Manufacturer Part Number
MC68HC908GR4
Description
Microcontrollers
Manufacturer
MOTOROLA [Motorola, Inc]
Datasheet
1.MC68HC908GR4.pdf
(408 pages)
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Computer Operating Properly (COP)
9.4.6 Reset Vector Fetch
9.4.7 COPD (COP Disable)
9.4.8 COPRS (COP Rate Select)
9.5 COP Control Register
9.6 Interrupts
Technical Data
136
Address: $FFFF
A reset vector fetch occurs when the vector address appears on the data
bus. A reset vector fetch clears the COP prescaler.
The COPD signal reflects the state of the COP disable bit (COPD) in the
configuration register. See
The COPRS signal reflects the state of the COP rate select bit (COPRS)
in the configuration register. See
The COP control register is located at address $FFFF and overlaps the
reset vector. Writing any value to $FFFF clears the COP counter and
starts a new timeout period. Reading location $FFFF returns the low
byte of the reset vector.
The COP does not generate CPU interrupt requests.
Reset:
Read:
Write:
Freescale Semiconductor, Inc.
For More Information On This Product,
Bit 7
Computer Operating Properly (COP)
Figure 9-2. COP Control Register (COPCTL)
Go to: www.freescale.com
6
5
Configuration Register
Low byte of reset vector
Unaffected by reset
Clear COP counter
Configuration Register
4
3
MC68HC908GR8 — Rev 4.0
(CONFIG).
2
(CONFIG).
1
MOTOROLA
Bit 0
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