PIC18F24J11 MICROCHIP [Microchip Technology], PIC18F24J11 Datasheet - Page 341

• Manufacturer Part Number: PIC18F24J11
• Description: 28/44-Pin, Low-Power, High-Performance USB Microcontrollers with nanoWatt XLP Technology
• Manufacturer: MICROCHIP [Microchip Technology]

TABLE 20-6:
20.2.4
During Sleep mode, all clocks to the EUSART are
suspended. Because of this, the BRG is inactive and a
proper byte reception cannot be performed. The
auto-wake-up feature allows the controller to wake-up
due to activity on the RXx/DTx line while the EUSART
is operating in Asynchronous mode.
The auto-wake-up feature is enabled by setting the
WUE bit (BAUDCONx<1>). Once set, the typical
receive sequence on RXx/DTx is disabled and the
EUSART remains in an Idle state, monitoring for a
wake-up event independent of the CPU mode. A
wake-up event consists of a high-to-low transition on
the RXx/DTx line. (This coincides with the start of a
Sync Break or a Wake-up Signal character for the
LIN/J2602 protocol.)
Following a wake-up event, the module generates an
RCxIF interrupt. The interrupt is generated synchro-
nously to the Q clocks in normal operating modes
(Figure
Sleep mode
cleared by reading the RCREGx register.
 2011 Microchip Technology Inc.
INTCON
PIR1
PIE1
IPR1
PIR3
PIE3
IPR3
RCSTAx
RCREGx
TXSTAx
BAUDCONx ABDOVF
SPBRGHx
SPBRGx
Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous reception.
Note 1:
Name
20-8) and asynchronously if the device is in
These bits are only available on 44-pin devices.
AUTO-WAKE-UP ON SYNC BREAK
CHARACTER
(Figure
EUSARTx Receive Register
EUSARTx Baud Rate Generator Register High Byte
EUSARTx Baud Rate Generator Register Low Byte
GIE/GIEH PEIE/GIEL TMR0IE
PMPIE
PMPIP
PMPIF
SSP2IE
SSP2IP
SSP2IF
CSRC
SPEN
Bit 7
REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
20-9). The interrupt condition is
(1)
(1)
(1)
BCL2IE
BCL2IP
BCL2IF
RCIDL
ADIE
ADIP
ADIF
Bit 6
RX9
TX9
RXDTP
RC1IE
RC1IP
RC2IE
RC2IP
RC1IF
RC2IF
SREN
TXEN
Bit 5
TXCKP
INT0IE
CREN
TX1IF
TX1IE
TX1IP
TX2IF
TX2IE
TX2IP
SYNC
Bit 4
PIC18F46J11 FAMILY
TMR4IF
TMR4IE
TMR4IP
SSP1IE
SSP1IP
ADDEN
SSP1IF
SENDB
BRG16
RBIE
Bit 3
CTMUIE TMR3GIE
CTMUIP TMR3GIP
CTMUIF TMR3GIF
TMR0IF
CCP1IF
CCP1IE
CCP1IP
BRGH
FERR
Bit 2
—
TMR2IE
TMR2IP
TMR2IF
INT0IF
OERR
TRMT
WUE
Bit 1
TMR1IF
TMR1IE
TMR1IP
RTCCIF
RTCCIE
RTCCIP
ABDEN
RX9D
TX9D
RBIF
DS39932D-page 341
Bit 0
on Page:
Values
Reset
69
72
72
72
72
72
72
72
72
72
73
72
72