PIC18F24J11 MICROCHIP [Microchip Technology], PIC18F24J11 Datasheet - Page 172

• Manufacturer Part Number: PIC18F24J11
• Description: 28/44-Pin, Low-Power, High-Performance USB Microcontrollers with nanoWatt XLP Technology
• Manufacturer: MICROCHIP [Microchip Technology]

PIC18F46J11 FAMILY
11.1
The PMP module has a total of 14 Special Function
Registers (SFRs) for its operation, plus one additional
register to set configuration options. Of these, eight
registers are used for control and six are used for PMP
data transfer.
11.1.1
The eight PMP Control registers are:
• PMCONH and PMCONL
• PMMODEH and PMMODEL
• PMSTATL and PMSTATH
• PMEH and PMEL
REGISTER 11-1:
DS39932D-page 172
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6-5
bit 4-3
bit 2
bit 1
bit 0
Note 1:
PMPEN
R/W-0
Module Registers
This register is only available in 44-pin devices.
CONTROL REGISTERS
PMPEN: Parallel Master Port Enable bit
1 = PMP enabled
0 = PMP disabled, no off-chip access performed
Unimplemented: Read as ‘0’
ADRMUX<1:0>: Address/Data Multiplexing Selection bits
11 = Reserved
10 = All 16 bits of address are multiplexed on PMD<7:0> pins
01 = Lower 8 bits of address are multiplexed on PMD<7:0> pins (only eight bits of address are
00 = Address and data appear on separate pins (only eight bits of address are available in this mode)
PTBEEN: Byte Enable Port Enable bit (16-Bit Master mode)
1 = PMBE port enabled
0 = PMBE port disabled
PTWREN: Write Enable Strobe Port Enable bit
1 = PMWR/PMENB port enabled
0 = PMWR/PMENB port disabled
PTRDEN: Read/Write Strobe Port Enable bit
1 = PMRD/PMWR port enabled
0 = PMRD/PMWR port disabled
U-0
—
available in this mode)
PMCONH: PARALLEL PORT CONTROL REGISTER HIGH BYTE (BANKED F5Fh)
W = Writable bit
‘1’ = Bit is set
U-0
—
ADRMUX1
R/W-0
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
ADRMUX0
R/W-0
The
Register
ing turning the module on or off. They also configure
address multiplexing and control strobe configuration.
The
Register
modes, the data width and interrupt generation.
The PMEH and PMEL registers
Register
hardware (I/O pin) level.
The
Register
input and output buffers, depending on the operating
mode.
PMMODE
PMSTAT
PMCON
11-2) control basic module operations, includ-
11-4) configure the various Master and Slave
11-6) configure the module’s operation at the
11-6) provide status flags for the module’s
PTBEEN
R/W-0
registers
registers
registers
 2011 Microchip Technology Inc.
x = Bit is unknown
PTWREN
R/W-0
(Register 11-1
(Register 11-5
(Register 11-3
(Register 11-5
PTRDEN
R/W-0
bit 0
and
and
and
and
(1)