PIC18F24J11 MICROCHIP [Microchip Technology], PIC18F24J11 Datasheet - Page 223

• Manufacturer Part Number: PIC18F24J11
• Description: 28/44-Pin, Low-Power, High-Performance USB Microcontrollers with nanoWatt XLP Technology
• Manufacturer: MICROCHIP [Microchip Technology]

15.6
The TMR3 register pair (TMR3H:TMR3L) increments
from 0000h to FFFFh and overflows to 0000h. The
Timer3 interrupt, if enabled, is generated on overflow
and is latched in interrupt flag bit, TMR3IF (PIR2<1>).
This interrupt can be enabled or disabled by setting or
clearing the Timer3 Interrupt Enable bit, TMR3IE
(PIE2<1>).
15.7
If ECCP1 or ECCP2 is configured to use Timer3 and to
generate a Special Event Trigger in Compare mode
(CCPxM<3:0> = 1011), this signal will reset Timer3.
TABLE 15-3:
 2011 Microchip Technology Inc.
INTCON
PIR2
PIE2
IPR2
TMR3L
TMR3H
T1CON
T3CON
T3GCON
TCLKCON
PIR3
PIE3
IPR3
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer3 module.
Name
Timer3 Interrupt
Resetting Timer3 Using the ECCP
Special Event Trigger
Timer3 Register Low Byte
Timer3 Register High Byte
TMR1CS1 TMR1CS0 T1CKPS1 T1CKPS0 T1OSCEN T1SYNC
TMR3CS1 TMR3CS0 T3CKPS1 T3CKPS0
GIE/GIEH PEIE/GIEL TMR0IE
TMR3GE
OSCFIF
OSCFIE
OSCFIP
SSP2IF
SSP2IE
SSP2IP
Bit 7
—
REGISTERS ASSOCIATED WITH TIMER3 AS A TIMER/COUNTER
T3GPOL
BCL2IE
BCL2IP
BCL2IF
CM2IE
CM2IP
CM2IF
Bit 6
—
T3GTM
CM1IF
CM1IE
CM1IP
RC2IF
RC2IE
RC2IP
Bit 5
—
T3GSPM
T1RUN
INT0IE
TX2IF
TX2IE
TX2IP
Bit 4
—
—
—
T3DONE
T3GGO/
TMR4IE
TMR4IP
TMR4IF
PIC18F46J11 FAMILY
BCL1IF
BCL1IE
BCL1IP
RBIE
The trigger from ECCP2 will also start an A/D conver-
sion if the A/D module is enabled (see
“Special Event Trigger”
The module must be configured as either a timer or
synchronous counter to take advantage of this feature.
When used this way, the CCPRxH:CCPRxL register
pair effectively becomes a Period register for Timer3.
If Timer3 is running in Asynchronous Counter mode,
the Reset operation may not work.
In the event that a write to Timer3 coincides with a
Special Event Trigger from an ECCP module, the write
will take precedence.
Bit 3
—
—
Note:
T3SYNC
CTMUIE
CTMUIP
T3GVAL
CTMUIF
TMR0IF
LVDIF
LVDIE
LVDIP
Bit 2
The Special Event Triggers from the
ECCPx module will not set the TMR3IF
interrupt flag bit (PIR1<0>).
—
TMR3GIF
TMR3GIE
TMR3GIP
T3GSS1
T3CCP2
TMR3IE
TMR3IP
TMR3IF
INT0IF
RD16
RD16
Bit 1
for more information).
TMR1ON
TMR3ON
T3GSS0
T3CCP1
RTCCIE
RTCCIP
CCP2IE
CCP2IP
RTCCIF
CCP2IF
RBIF
Bit 0
DS39932D-page 223
Section 18.3.4
on Page:
Values
Reset
90
92
92
92
93
93
91
93
92
94
92
92
92