PIC18F2480 MICROCHIP [Microchip Technology], PIC18F2480 Datasheet - Page 67

• Manufacturer Part Number: PIC18F2480
• Description: 28/40/44-Pin Enhanced Flash Microcontrollers with ECAN Technology, 10-Bit A/D and nanoWatt Technology
• Manufacturer: MICROCHIP [Microchip Technology]

5.2
5.2.1
The microcontroller clock input, whether from an inter-
nal or external source, is internally divided by four to
generate four non-overlapping quadrature clocks (Q1,
Q2, Q3 and Q4). Internally, the Program Counter (PC)
is incremented on every Q1; the instruction is fetched
from the program memory and latched into the Instruc-
tion Register (IR) during Q4. The instruction is decoded
and executed during the following Q1 through Q4. The
clocks and instruction execution flow are shown in
Figure 5-3.
FIGURE 5-3:
EXAMPLE 5-3:
 2004 Microchip Technology Inc.
1. MOVLW 55h
2. MOVWF PORTB
3. BRA
4. BSF
5. Instruction @ address SUB_1
Note:
OSC2/CLKO
(RC mode)
PIC18 Instruction Cycle
SUB_1
CLOCKING SCHEME
PORTA, BIT3 (Forced NOP)
OSC1
All instructions are single cycle, except for any program branches. These take two cycles since the
fetch instruction is “flushed” from the pipeline while the new instruction is being fetched and then
executed.
PC
Q1
Q2
Q3
Q4
Q1
CLOCK/INSTRUCTION CYCLE
INSTRUCTION PIPELINE FLOW
Execute INST (PC – 2)
Fetch INST (PC)
Q2
Fetch 1
T
PC
CY
Q3
0
Q4
Execute 1
Fetch 2
PIC18F2480/2580/4480/4580
T
CY
Q1
1
Preliminary
Fetch INST (PC + 2)
Execute INST (PC)
Q2
Execute 2
Fetch 3
PC + 2
T
CY
Q3
2
5.2.2
An “Instruction Cycle” consists of four Q cycles: Q1
through Q4. The instruction fetch and execute are
pipelined in such a manner that a fetch takes one
instruction cycle, while the decode and execute take
another instruction cycle. However, due to the
pipelining, each instruction effectively executes in one
cycle. If an instruction causes the program counter to
change (e.g., GOTO), then two cycles are required to
complete the instruction (Example 5-3).
A fetch cycle begins with the program counter
incrementing in Q1.
In the execution cycle, the fetched instruction is latched
into the Instruction Register (IR) in cycle Q1. This
instruction is then decoded and executed during the
Q2, Q3 and Q4 cycles. Data memory is read during Q2
(operand read) and written during Q4 (destination
write).
Q4
Execute 3
Fetch 4
T
CY
INSTRUCTION FLOW/PIPELINING
3
Q1
Execute INST (PC + 2)
Fetch INST (PC + 4)
Fetch SUB_1 Execute SUB_1
Flush (NOP)
Q2
PC + 4
T
CY
Q3
4
Q4
DS39637A-page 65
T
CY
Internal
Phase
Clock
5