PIC18F2480 MICROCHIP [Microchip Technology], PIC18F2480 Datasheet - Page 184

• Manufacturer Part Number: PIC18F2480
• Description: 28/40/44-Pin Enhanced Flash Microcontrollers with ECAN Technology, 10-Bit A/D and nanoWatt Technology
• Manufacturer: MICROCHIP [Microchip Technology]

PIC18F2480/2580/4480/4580
16.4.6
In half-bridge applications where all power switches are
modulated at the PWM frequency at all times, the power
switches normally require more time to turn off than to
turn on. If both the upper and lower power switches are
switched at the same time (one turned on and the other
turned off), both switches may be on for a short period of
time until one switch completely turns off. During this
brief interval, a very high current (shoot-through current)
may flow through both power switches, shorting the
bridge supply. To avoid this potentially destructive
shoot-through current from flowing during switching,
turning on either of the power switches is normally
delayed to allow the other switch to completely turn off.
In the Half-Bridge Output mode, a digitally program-
mable dead-band delay is available to avoid
shoot-through current from destroying the bridge
power switches. The delay occurs at the signal transi-
tion from the non-active state to the active state. See
Figure 16-4 for illustration. Bits PDC6:PDC0 of the
ECCP1DEL register (Register 16-2) set the delay
period in terms of microcontroller instruction cycles
(T
PIC18F2X80 devices, as the standard CCP module
does not support half-bridge operation.
16.4.7
When the CCP1 is programmed for any of the Enhanced
PWM modes, the active output pins may be configured
for auto-shutdown. Auto-shutdown immediately places
the Enhanced PWM output pins into a defined shutdown
state when a shutdown event occurs.
REGISTER 16-2:
DS39637A-page 182
CY
Note:
or 4 T
bit 7
bit 6-0
PROGRAMMABLE DEAD-BAND
DELAY
Programmable dead-band delay is not
implemented in PIC18F2X80 devices with
standard CCP modules.
ENHANCED PWM AUTO-SHUTDOWN
OSC
). These bits are not available on
ECCP1DEL: PWM CONFIGURATION REGISTER
bit 7
PRSEN: PWM Restart Enable bit
1 = Upon auto-shutdown, the ECCPASE bit clears automatically once the shutdown event
0 = Upon auto-shutdown, ECCPASE must be cleared in software to restart the PWM
PDC6:PDC0: PWM Delay Count bits
Delay time, in number of F
a PWM signal to transition to active.
Legend:
R = Readable bit
-n = Value at POR
PRSEN
R/W-0
Note 1: Reserved on PIC18F2X80 devices; maintain these bits clear.
goes away; the PWM restarts automatically
PDC6
R/W-0
(1)
PDC5
R/W-0
OSC
Preliminary
W = Writable bit
‘1’ = Bit is set
/4 (4 * T
(1)
PDC4
(1)
R/W-0
OSC
comparator
A shutdown event can be caused by either of the
RB0/INT0/FLT0/AN10 pin, or any combination of these
three sources. The comparators may be used to monitor
a voltage input proportional to a current being monitored
in the bridge circuit. If the voltage exceeds a threshold,
the comparator switches state and triggers a shutdown.
Alternatively, a digital signal on the INT0 pin can also
trigger a shutdown. The auto-shutdown feature can be
disabled by not selecting any auto-shutdown sources.
The auto-shutdown sources to be used are selected
using the ECCPAS2:ECCPAS0 bits (bits<6:4> of the
ECCP1AS register).
When a shutdown occurs, the output pins are
asynchronously placed in their shutdown states,
specified
PSS1BD1:PSS1BD0
Each pin pair (P1A/P1C and P1B/P1D) may be set to
drive high, drive low or be tri-stated (not driving). The
ECCPASE bit (ECCP1AS<7>) is also set to hold the
Enhanced PWM outputs in their shutdown states.
The ECCPASE bit is set by hardware when a shutdown
event occurs. If automatic restarts are not enabled, the
ECCPASE bit is cleared by firmware when the cause of
the shutdown clears. If automatic restarts are enabled,
the ECCPASE bit is automatically cleared when the
cause of the auto-shutdown has cleared.
If the ECCPASE bit is set when a PWM period begins,
the PWM outputs remain in their shutdown state for that
entire PWM period. When the ECCPASE bit is cleared,
the PWM outputs will return to normal operation at the
beginning of the next PWM period.
Note:
) cycles, between the scheduled and actual time for
(1)
PDC3
R/W-0
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
Writing to the ECCPASE bit is disabled
while a shutdown condition is active.
by
modules,
(1)
the
PDC2
R/W-0
 2004 Microchip Technology Inc.
bits
(1)
a
PSSAC1:PSSAC0
(ECCPAS3:ECCPAS0).
low
x = Bit is unknown
PDC1
R/W-0
level
(1)
PDC0
R/W-0
on
bit 0
(1)
and
the