PIC18F2480 MICROCHIP [Microchip Technology], PIC18F2480 Datasheet - Page 479

• Manufacturer Part Number: PIC18F2480
• Description: 28/40/44-Pin Enhanced Flash Microcontrollers with ECAN Technology, 10-Bit A/D and nanoWatt Technology
• Manufacturer: MICROCHIP [Microchip Technology]

 2004 Microchip Technology Inc.
I
I
I
I
I
I
I
I
I
I
I
Master SSP I
Master SSP I
Parallel Slave Port (PIC18F4480/4580) ................... 440
Parallel Slave Port (PSP) Read ............................... 145
Parallel Slave Port (PSP) Write ............................... 145
PWM Auto-Shutdown (PRSEN = 0,
PWM Auto-Shutdown (PRSEN = 1,
PWM Direction Change ........................................... 181
PWM Direction Change at Near
PWM Output ............................................................ 169
Repeat Start Condition ............................................. 216
Reset, Watchdog Timer (WDT),
Send Break Character Sequence ............................ 241
Slave Synchronization ............................................. 193
Slow Rise Time (MCLR Tied to V
SPI Mode (Master Mode) ......................................... 192
SPI Mode (Slave Mode with CKE = 0) ..................... 194
SPI Mode (Slave Mode with CKE = 1) ..................... 194
Stop Condition Receive or Transmit Mode .............. 220
Synchronous Reception
Synchronous Transmission ...................................... 242
Synchronous Transmission (Through TXEN) .......... 243
Time-out Sequence on POR w/PLL
Time-out Sequence on Power-up
Time-out Sequence on Power-up
Time-out Sequence on Power-up
Timer0 and Timer1 External Clock .......................... 438
Transition for Entry to Idle Mode ................................ 38
Transition for Entry to SEC_RUN Mode .................... 35
Transition for Entry to Sleep Mode ............................ 37
Transition for Two-Speed Start-up
Transition for Wake from Idle to Run Mode ............... 38
Transition for Wake from Sleep (HSPLL) ................... 37
Transition from RC_RUN Mode to
Transition from SEC_RUN Mode to
Transition to RC_RUN Mode ..................................... 36
2
2
2
2
2
2
2
2
2
2
2
C Bus Data ............................................................ 445
C Bus Start/Stop Bits ............................................. 445
C Master Mode (7 or 10-Bit Transmission) ........... 218
C Master Mode (7-Bit Reception) .......................... 219
C Slave Mode (10-Bit Reception, SEN = 0) .......... 204
C Slave Mode (10-Bit Reception, SEN = 1) .......... 209
C Slave Mode (10-Bit Transmission) ..................... 205
C Slave Mode (7-Bit Reception, SEN = 0) ............ 202
C Slave Mode (7-Bit Reception, SEN = 1) ............ 208
C Slave Mode (7-Bit Transmission) ....................... 203
C Slave Mode General Call Address
Sequence (7 or 10-Bit Address Mode) ............ 210
Auto-Restart Disabled) .................................... 184
Auto-Restart Enabled) ..................................... 184
100% Duty Cycle ............................................. 181
Oscillator Start-up Timer (OST) and
Power-up Timer (PWRT) ................................. 437
V
(Master Mode, SREN) ..................................... 244
Enabled (MCLR Tied to V
(MCLR Not Tied to V
(MCLR Not Tied to V
(MCLR Tied to V
(INTOSC to HSPLL) ........................................ 354
PRI_RUN Mode ................................................. 36
PRI_RUN Mode (HSPLL) .................................. 35
DD
Rise > T
2
2
C Bus Data ........................................ 447
C Bus Start/Stop Bits ........................ 447
PWRT
DD
) ............................................ 47
, V
DD
DD
DD
), Case 1 ....................... 46
), Case 2 ....................... 46
Rise T
DD
DD
) ............................. 47
,
PWRT
) .............. 46
PIC18F2480/2580/4480/4580
Preliminary
Timing Diagrams and Specifications ............................... 434
Top-of-Stack Access .......................................................... 62
TRISE Register
TSTFSZ ........................................................................... 401
Two-Speed Start-up ................................................. 343, 354
Two-Word Instructions
TXSTA Register
V
Voltage Reference Specifications .................................... 430
W
Watchdog Timer (WDT) ........................................... 343, 352
WCOL ...................................................... 215, 216, 217, 220
WCOL Status Flag ................................... 215, 216, 217, 220
WWW, On-Line Support ...................................................... 5
X
XORLW ........................................................................... 401
XORWF ........................................................................... 402
A/D Conversion Requirements ................................ 451
AC Characteristics
Capture/Compare/PWM Requirements ................... 439
CLKO and I/O Requirements ................................... 436
EUSART Synchronous Receive
EUSART Synchronous Transmission
Example SPI Mode Requirements
External Clock Requirements .................................. 434
High/Low-Voltage Detect Characteristics ................ 431
I
Master SSP I
Master SSP I
Parallel Slave Port Requirements
PLL Clock ................................................................ 435
Reset, Watchdog Timer, Oscillator
Timer0 and Timer1 External
PSPMODE Bit ......................................................... 138
Example Cases ......................................................... 66
BRGH Bit ................................................................. 231
Associated Registers ............................................... 353
Control Register ....................................................... 352
During Oscillator Failure .......................................... 355
Programming Considerations .................................. 352
2
C Bus Data Requirements (Slave Mode) .............. 446
Internal RC Accuracy ....................................... 435
Requirements .................................................. 449
Requirements .................................................. 449
Master Mode, CKE = 0 .................................... 441
Master Mode, CKE = 1 .................................... 442
Slave Mode, CKE = 0 ...................................... 443
Slave Mode, CKE = 1 ...................................... 444
Bits Requirements ........................................... 447
(PIC18F4480/4580) ......................................... 440
Start-up Timer, Power-up Timer
and Brown-out Reset Requirements ............... 437
Clock Requirements ........................................ 438
2
2
C Bus Data Requirements ................ 448
C Bus Start/Stop
DS39637A-page 477