PIC18F2331-E/ML MICROCHIP [Microchip Technology], PIC18F2331-E/ML Datasheet - Page 295

• Manufacturer Part Number: PIC18F2331-E/ML
• Description: 28/40/44-Pin Enhanced Flash Microcontrollers with nanoWatt Technology, High-Performance PWM and A/D
• Manufacturer: MICROCHIP [Microchip Technology]

BRA
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
 2010 Microchip Technology Inc.
Q Cycle Activity:
Before Instruction
After Instruction
operation
Decode
No
PC
PC
Q1
Read literal
operation
Unconditional Branch
[ label ] BRA
-1024  n  1023
(PC) + 2 + 2n  PC
None
Add the 2’s complement number, ‘2n’,
to the PC. Since the PC will have incre-
mented to fetch the next instruction, the
new address will be PC + 2 + 2n. This
instruction is a two-cycle instruction.
1
2
HERE
1101
No
Q2
‘n’
=
=
address (HERE)
address (Jump)
0nnn
BRA
operation
Process
n
Data
No
Q3
Jump
nnnn
operation
Write to
PIC18F2331/2431/4331/4431
PC
No
Q4
nnnn
BSF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
Before Instruction
After Instruction
Decode
FLAG_REG
FLAG_REG
Q1
register ‘f’
Bit Set f
[ label ] BSF
0  f  255
0  b  7
a [0,1]
1  f<b>
None
Bit ‘b’ in register, ‘f’, is set. If ‘a’ is ‘0’,
Access Bank will be selected, over-
riding the BSR value. If ‘a’ = 1, then the
bank will be selected as per the BSR
value.
1
1
BSF
Read
1000
Q2
=
=
0x0A
0x8A
FLAG_REG, 7
bbba
Process
f,b[,a]
Data
Q3
DS39616D-page 295
ffff
register ‘f’
Write
Q4
ffff