PIC18F2331-E/ML MICROCHIP [Microchip Technology], PIC18F2331-E/ML Datasheet - Page 162

• Manufacturer Part Number: PIC18F2331-E/ML
• Description: 28/40/44-Pin Enhanced Flash Microcontrollers with nanoWatt Technology, High-Performance PWM and A/D
• Manufacturer: MICROCHIP [Microchip Technology]

PIC18F2331/2431/4331/4431
17.2.1
The QEI module shares its input pins with the Input
Capture (IC) module. The inputs are mutually
exclusive; only the IC module or the QEI module (but
not both) can be enabled at one time. Also, because
the IC and QEI are multiplexed to the same input pins,
the programmable noise filters can be dedicated to one
module only.
REGISTER 17-2:
DS39616D-page 162
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5
bit 4-2
bit 1-0
Note 1:
R/W-0
VELM
2:
3:
4:
QEI must be enabled and in Index mode.
QEI mode select must be cleared (= 000) to enable CAP1, CAP2 or CAP3 inputs. If QEI and IC modules
are both enabled, QEI will take precedence.
Enabling one of the QEI operating modes remaps the IC Buffer registers, CAP1BUFH, CAP1BUFL,
CAP2BUFH, CAP2BUFL, CAP3BUFH and CAP3BUFL, as the VELRH, VELRL, POSCNTH, POSCNTL,
MAXCNTH and MAXCNTL registers (respectively) for the QEI.
The QERR bit must be cleared in software.
QEI CONFIGURATION
VELM: Velocity Mode bit
1 = Velocity mode disabled
0 = Velocity mode enabled
QERR: QEI Error bit
1 = Position counter overflow or underflow
0 = No overflow or underflow
UP/DOWN: Direction of Rotation Status bit
1 = Forward
0 = Reverse
QEIM<2:0>: QEI Mode bits
111 = Unused
110 = QEI enabled in 4x Update mode; position counter is reset on period match (POSCNT = MAXCNT)
101 = QEI enabled in 4x Update mode; INDX resets the position counter
100 = Unused
010 = QEI enabled in 2x Update mode; position counter is reset on period match (POSCNT = MAXCNT)
001 = QEI enabled in 2x Update mode; INDX resets the position counter
000 = QEI off
PDEC<1:0>: Velocity Pulse Reduction Ratio bits
11 = 1:64
10 = 1:16
01 = 1:4
00 = 1:1
QERR
R/W-0
QEICON: QUADRATURE ENCODER INTERFACE CONTROL REGISTER
(1)
W = Writable bit
‘1’ = Bit is set
UP/DOWN
R-0
(1)
(2,3)
QEIM2
R/W-0
(2,3)
(4)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
QEIM1
R/W-0
The operation of the QEI is controlled by the QEICON
Configuration register (see
Note:
(2,3)
In the event that both QEI and IC are
enabled, QEI will take precedence and IC
will remain disabled.
QEIM0
R/W-0
(2,3)
 2010 Microchip Technology Inc.
x = Bit is unknown
Register
PDEC1
R/W-0
17-2).
PDEC0
R/W-0
bit 0