MC68HC11F1CFN5 MOTOROLA [Motorola, Inc], MC68HC11F1CFN5 Datasheet - Page 36

• Manufacturer Part Number: MC68HC11F1CFN5
• Description: Technical Summary 8-Bit Microcontroller
• Manufacturer: MOTOROLA [Motorola, Inc]

PORTD — Port D Data Register
DDRD — Port D Data Direction Register
PORTE — Port E Data
GWOM — Port G Wired-OR Mode Option
36
OPT2 — System Configuration Option Register 2
RESET:
RESET:
RESET:
Alternate
Function
MOTOROLA
RESET
Function:
Alternate
NOTES:
For DDRx bits, 0 = input and 1 = output.
1. These bits are not present on the MC68HC11FC0 and will always read zero.
2. This bit is not present on the 64-pin QFP version of the MC68HC11FC0 and will always read zero.
U = Unaffected by rest.
PORTE is an input-only register. Reads return the digital state of the I/O pins, and writes have no effect.
On the MC68HC11F1, port E is shared with the analog-to-digital converter. (The A/D converter is not
present on the MC68HC11FC0.)
This bit affects all port G pins together.
0 = Port G outputs are normal CMOS outputs
1 = Port G outputs act as open-drain outputs
GWOM
PE7
Bit 7
Bit 7
Bit 7
AN7
Bit 7
—
U
0
0
0
0
0
When the SPI system is in slave mode, DDD5 has no meaning or effect. When the
SPI system is in master mode, DDD5 determines whether bit 5 of PORTD is an er-
ror detect input (DDD5 = 0) or a general-purpose output (DDD5 = 1). If the SPI sys-
tem is enabled and expects one or more of bits [4:2] to be inputs, those bits will be
inputs regardless of the state of the associated DDR bits. If one or more of bits [4:2]
are expected to be outputs, those bits will be outputs only if the associated DDR
bits are set.
1
CWOM
PE6
AN6
—
U
6
0
0
6
0
0
6
6
0
CLK4X
DDD5
PD5
PE5
AN5
SS
U
5
1
5
5
0
5
I
LIRDV
DDD4
PE4
SCK
PD4
AN4
4
0
U
4
4
0
4
I
2
NOTE
DDD3
MOSI
PD3
PE3
AN3
—
3
0
U
3
3
0
3
I
SPRBYP
DDD2
MISO
PD2
AN2
PE2
2
0
U
2
2
0
2
I
DDD1
PD1
AN1
TxD
PE1
—
1
0
U
1
1
0
1
I
MC68HC11F1/FC0
DDD0
Bit 0
PE0
MC68HC11FTS/D
Bit 0
PD0
RxD
Bit 0
Bit 0
AN0
—
0
U
0
I
1
$x00A
$x008
$x009
$x038