MC68HC11F1CFN5 MOTOROLA [Motorola, Inc], MC68HC11F1CFN5 Datasheet - Page 21

• Manufacturer Part Number: MC68HC11F1CFN5
• Description: Technical Summary 8-Bit Microcontroller
• Manufacturer: MOTOROLA [Motorola, Inc]

RBOOT — Read Bootstrap ROM
SMOD and MDA — Special Mode Select and Mode Select A
IRV — Internal Read Visibility
PSEL[3:0] — See 5.2 Reset and Interrupt Registers, page 27.
INIT — RAM and I/O Mapping (MC68HC11FC0 only)
RAM[5:0] — Internal RAM Map Position
REG[1:0] — Register Block Map Position
MC68HC11F1/FC0
MC68HC11FTS/D
RESET:
RBOOT is valid only when SMOD is set to one (special bootstrap or special test mode). RBOOT can
only be written in special modes but can be read anytime.
The initial value of SMOD is the inverse of the logic level present on the MODB pin at the rising edge
of reset. The initial value of MDA equals the logic level present on the MODA pin at the rising edge of
reset. These two bits can be read at any time. They can be written at any time in special modes. Neither
bit can be written in normal modes. SMOD cannot be set once it has been cleared. Refer to Table 8.
This bit can be read at any time. It can be written at any time in special modes, but only once in normal
modes. In single-chip and bootstrap modes, IRV has no meaning or effect.
The INIT register can be written only once in first 64 cycles out of reset in normal modes, or at any time
in special modes.
These bits determine the upper six bits of the RAM address and allow mapping of the RAM to any one-
Kbyte boundary.
These bits determine the location of the register block, as shown in Table 9.
0 = Boot loader ROM disabled and not in memory map
1 = Boot loader ROM enabled and in memory map at $BF00–$BFFF
0 = Internal reads not visible
1 = Data from internal reads is driven on the external data bus
MODB
RAM5
Bit 7
1
1
0
0
0
Input Pins
The register diagram above applies to the MC68HC11FC0 only. A diagram and bit
descriptions of the INIT register in the MC68HC11F1 are provided elsewhere in
this section.
MODA
RAM4
0
1
0
1
6
0
Table 8 Hardware Mode Select Summary
Single Chip
Expanded
Special Bootstrap
Special Test
Mode Description
RAM3
Table 9 Register Block Location
REG[1:0]
5
0
0 0
0 1
1 0
1 1
RAM2
4
0
Register Block Address
NOTE
$0000 – $005F
$1000 – $105F
$2000 – $205F
$3000 – $305F
Control Bits in HPRIO (Latched at Reset)
RAM1
RBOOT
3
0
0
0
1
0
RAM0
2
0
SMOD
0
0
1
1
REG1
1
0
MDA
REG0
Bit 0
0
1
0
1
1
MOTOROLA
$x03D
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