DP83932C NSC [National Semiconductor], DP83932C Datasheet - Page 84

• Manufacturer Part Number: DP83932C
• Description: MHz SONICTM Systems-Oriented Network Interface Controller
• Manufacturer: NSC [National Semiconductor]

Number
T43
T44
T45
T46
T51
T52
T53
T55
T55b
7 0 AC and DC Specifications
BUS REQUEST TIMING BMODE
Note 1 A block transfer by the SONIC can be pre-empted from the bus by deasserting HLDA provided HLDA is deasserted T46 before the rising edge of the last
T2 in the current access
Note 2 The assertion edge for HOLD is dependent upon the PH bit in the DCR2 The default situation is shown wih a solid line in the timing diagram T43 and T44
apply for both modes Also if HLDA is asserted when the SONIC wants to acquire the bus HOLD will not be asserted until HLDA has been deasserted first
Note 3 S
Note 4 This timing value includes an RC delay inherent in the test measurement These signals typically TRI-STATE 7 ns earlier enabling other devices to drive
these lines without contention
Note 5 The HLDA signal is sampled by the SONIC on each rising edge of BSCK The maximum setup time is ((BSCK period–T45 min spec)–5ns) The HLDA
max setup time is for information only and is not tested
k
2 0
l
BSCK to HOLD High (Note 2)
BSCK to HOLD Low (Note 2)
HLDA Synchronous Setup Time to BSCK (Note 5)
HLDA Synchronous Deassert Setup Time (Note 1)
BSCK to Address ADS MWR DS ECS
USR
(Note 4)
BSCK to Data TRI-STATE
BSCK to USR
BSCK to Bus Status Valid
S
will indicate IDLE at the end of T2 if the last operation is a read operation or at the end of Th if the last operation is a write operation
k
2 0
k
1 0
l
Hold from BSCK
l
and EXUSR
k
1 0
l
Parameter
e
or EXUSR
0
k
3 0
l
TRI-STATE
k
3 0
(Continued)
l
Valid
84
Min
7
7
3
20 MHz
Max
18
19
34
34
34
29
Min
6
6
3
25 MHz
Max
16
17
32
32
32
27
Min
5
5
3
33 MHz
Max
14
15
30
30
30
25
TL F 10492 – 67
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns