DP83932C NSC [National Semiconductor], DP83932C Datasheet - Page 55

• Manufacturer Part Number: DP83932C
• Description: MHz SONICTM Systems-Oriented Network Interface Controller
• Manufacturer: NSC [National Semiconductor]

Figure 5-7 illustrates the SONIC’s transitions through mem-
5 0 Bus Interface
5 4 3 1 Bus Status Transitions
When the SONIC acquires the bus it only transfers data
to from a single area in memory (i e TDA TBA RDA RBA
RRA or CDA) Thus the bus status pins remain stable for
the duration of the block transfer cycle with the following
three exceptions 1) If the SONIC is accessed during a block
transfer S2–S0 indicates bus idle during the register ac-
cess then returns to the previous status 2) If the SONIC
finishes writing the Source Address during a block transfer
S2 –S0 changes from 0 1 0 to 0 1 1 3) During an RDA
access between the RXpkt seq no and RXpkt link access
and between the RXpkt link and RXpkt in use access
S2 –S0 will respectively indicate idle 1 1 1 for 2 or 1 bus
clocks Status will be valid on the falling edge of AS or rising
edge of ADS
ory during the process of transmission and reception Dur-
ing transmission the SONIC reads the descriptor informa-
tion from the TDA and then transmits data of the packet
from the TBA The SONIC moves back and forth between
the TDA and TBA until all fragments and packets are trans-
mitted During reception the SONIC takes one of two paths
In the first case (path A) when the SONIC detects EOL
from the previous reception it buffers the accepted packet
into the RBA and then writes the descriptor information to
the RDA If the RBA becomes depleted (i e RBWC0 1
EOBC) it moves to the RRA to read a resource descriptor
In the second case (path B) when the SONIC detects
EOL
e
1 from the previous reception
(Continued)
it rereads the
FIGURE 5-7 Bus Status Transitions
e
k
0
55
RXpkt link field to determine if the system has reset the EOL
bit since the last reception If it has the SONIC buffers the
packet as in the first case Otherwise it rejects the packet
and returns to idle
5 4 4 Bus Mode Compatibility
For compatibility with different microprocessor and bus ar-
chitectures the SONIC operates in one of two modes (set
by the BMODE pin) called the National Intel or little endian
mode (BMODE tied low) and the Motorola or big endian
mode (BMODE tied high) The definitions for several pins
change depending on the mode the SONIC is in Table 5-3
shows these changes These modes affect both master and
slave bus operations with the SONIC
BR HOLD
BG HLDA
MRW MWR
SRW SWR
DSACK0 RDYi
DSACK1 RDYo
AS ADS
INT INT
Pin Name
TABLE 5-3 Bus Mode Compatibility
(National Intel)
HOLD
HLDA
MWR
SWR
RDYi
RDYo
ADS
INT
BMODE
e
0
BMODE
BR
BG
MRW
SRW
DSACK0
DSACK1
AS
INT
(Motorola)
TL F 10492 – 29
e
1