DP83932C NSC [National Semiconductor], DP83932C Datasheet - Page 62

• Manufacturer Part Number: DP83932C
• Description: MHz SONICTM Systems-Oriented Network Interface Controller
• Manufacturer: NSC [National Semiconductor]

5-18 and 5-19 ) data is driven on the rising edge of T1 If
5 0 Bus Interface
During read cycles ( Figures 5-16 and 5-17 ) data (D31-D0)
is latched on the rising edge at the end of T2 and DS is
asserted at the falling edge of T1 For write cycles ( Figures
there are wait states inserted DS is asserted on the falling
edge of the first T2(wait) DS is not asserted for zero wait
state write cycles The SONIC terminates the memory cycle
by deasserting DS at the falling edge of T2
Note If the setup time for RDYi is met during T1 the full asynchronous bus
cycle will take only 2 bus clocks This may be an unwanted situation
If so RDYi should be deasserted during T1
FIGURE 5-18 Memory Write BMODE
FIGURE 5-19 Memory Write BMODE
(Continued)
62
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e
5 4 6 Bus Exceptions (Bus Retry)
The SONIC provides the capability of handling errors during
the execution of the bus cycle ( Figure 5-20 )
The system asserts BRT (bus retry) to force the SONIC to
repeat the current memory cycle When the SONIC detects
the assertion of BRT it completes the memory cycle at the
end of T2 and gets off the bus by deasserting BGACK or
HOLD Then if Latched Bus Retry mode is not set (LBR in
the Data Configuration Register Section 4 3 2) the SONIC
requests the bus again to retry the same memory cycle If
0 Asynchronous (1 Wait-State)
0 Asynchronous (2 Wait-State)
TL F 10492– 42
TL F 10492 – 43