DP83932C NSC [National Semiconductor], DP83932C Datasheet - Page 61

• Manufacturer Part Number: DP83932C
• Description: MHz SONICTM Systems-Oriented Network Interface Controller
• Manufacturer: NSC [National Semiconductor]

5 0 Bus Interface
5 4 5 5 Memory Cycle for BMODE
Mode
On the rising edge of T1 the SONIC asserts ADS and ECS
to indicate that the memory cycle is starting The address
(A31-A1) bus status (S2-S0) and the direction strobe
(MWR) are driven and do not change for the remainder of
the memory cycle On the falling edge of T1 the SONIC
deasserts ECS ADS is deasserted on the rising edge of T2
FIGURE 5-16 Memory Read BMODE
FIGURE 5-17 Memory Read BMODE
(Continued)
e
0 Asynchronous
61
e
e
In Asynchronous mode RDYi is asynchronously sampled
on the falling edge of both T1 and T2 RDYi does not need
to be synchronized to the bus clock because the chip al-
ways resolves these signals to either a high or low state
Meeting the setup time for RDYi guarantees that the SONIC
will terminate the memory cycle 1 5 bus clocks after RDYi
was sampled T2 states will be repeated until RDYi is sam-
pled properly in a low state (see note on following page)
0 Asynchronous (1 Wait-State)
0 Asynchronous (2 Wait-State)
TL F 10492– 44
TL F 10492 – 45