MPC8358E_11 FREESCALE [Freescale Semiconductor, Inc], MPC8358E_11 Datasheet - Page 91

• Manufacturer Part Number: MPC8358E_11
• Description: PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

24.5
The device drivers are characterized over process, voltage, and temperature. For all buses, the driver is a
push-pull single-ended driver type (open drain for I
To measure Z
or GND. Then, the value of each resistor is varied until the pad voltage is OV
output impedance is the average of two components, the resistances of the pull-up and pull-down devices.
When data is held high, SW1 is closed (SW2 is open) and R
OV
other in value. Then, Z
The value of this resistance and the strength of the driver’s current source can be found by making two
measurements. First, the output voltage is measured while driving logic 1 without an external differential
termination resistor. The measured voltage is V
while driving logic 1 with an external precision differential termination resistor of value R
measured voltage is V
R
Table 77
nominal OV
Freescale Semiconductor
term
DD
Impedance
× (V
/2. R
MPC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 3
R
R
summarizes the signal impedance targets. The driver impedance are targeted at minimum V
N
P
Output Buffer DC Impedance
1
P
/V
DD
then becomes the resistance of the pull-up devices. R
0
2
for the single-ended drivers, an external resistor is connected from the chip pad to OV
, 105°C.
– 1). The drive current is then I
Control, Configuration, Power
Local Bus, Ethernet, DUART,
2
0
= 1/(1/R
= (R
P
Management
+ R
42 Target
42 Target
Figure 55. Driver Impedance Measurement
1
Data
+ 1/R
N
Table 77. Impedance Characteristics
)/2.
2
)) × I
source
1
source
= R
. Solving for the output impedance gives R
2
source
C).
= V
25 Target
25 Target
1
PCI
× I
/R
Pad
P
R
source
R
source
is trimmed until the voltage at the pad equals
OV
OGND
N
P
DD
P
. Second, the output voltage is measured
.
and R
SW2
SW1
DDR DRAM
20 Target
20 Target
N
are designed to be close to each
DD
/2 (see
System Design Information
Symbol
Figure
Z
Z
0
0
term
source
. The
55). The
Unit
=
W
W
DD
DD
91
,