MPC8358E_11 FREESCALE [Freescale Semiconductor, Inc], MPC8358E_11 Datasheet - Page 78

• Manufacturer Part Number: MPC8358E_11
• Description: PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Clocking
22.2
RCWL[COREPLL] selects the ratio between the internal coherent system bus clock (csb_clk) and the e300
core clock (core_clk).
in
78
1
2
CFG_CLKIN_DIV is only used for host mode; CLKIN must be tied low and CFG_CLKIN_DIV must be pulled down (low) in
agent mode.
CLKIN is the input clock in host mode; PCI_CLK is the input clock in agent mode.
Table 71
CFG_CLKIN_DIV
at Reset
MPC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 3
High
High
High
High
High
High
High
High
High
High
High
Core PLL Configuration
should be considered reserved.
1
Table 71
0–1
nn
00
01
10
11
00
01
10
RCWL[COREPLL]
SPMF
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0000
Table 70. CSB Frequency Options (continued)
shows the encodings for RCWL[COREPLL]. COREPLL values not listed
0000
0001
0001
0001
0001
0001
0001
0001
2–5
Table 71. e300 Core PLL Configuration
Input Clock Ratio
6
n
0
0
0
0
1
1
1
csb_clk :
10:1
11:1
12:1
13:1
14:1
15:1
16:1
6:1
7:1
8:1
9:1
clocks core directly)
core_clk : csb_clk
(PLL off, csb_clk
PLL bypassed
Ratio
1.5:1
1.5:1
1.5:1
2
1:1
1:1
1:1
1:1
16.67
clocks core directly)
Input Clock Frequency (MHz)
(PLL off, csb_clk
PLL bypassed
csb_clk Frequency (MHz)
VCO divider
25
÷
÷
÷
÷
÷
÷
÷
2
4
8
8
2
4
8
Freescale Semiconductor
33.33
200
233
2
66.67