MPC8358E_11 FREESCALE [Freescale Semiconductor, Inc], MPC8358E_11 Datasheet - Page 89

• Manufacturer Part Number: MPC8358E_11
• Description: PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

23.3.1
When heat sink is used, the junction temperature is determined from a thermocouple inserted at the
interface between the case of the package and the interface material. A clearance slot or hole is normally
required in the heat sink. Minimizing the size of the clearance is important to minimize the change in
thermal performance caused by removing part of the thermal interface to the heat sink. Because of the
experimental difficulties with this technique, many engineers measure the heat sink temperature and then
back calculate the case temperature using a separate measurement of the thermal resistance of the
interface. From this case temperature, the junction temperature is determined from the junction-to-case
thermal resistance.
where:
24 System Design Information
This section provides electrical and thermal design recommendations for successful application of the
MPC8358E. Additional information can be found in MPC8360E/MPC8358E PowerQUICC Design
Checklist (AN3097).
24.1
The device includes two PLLs, as follows.
24.2
Each of the PLLs listed above is provided with power through independent power supply pins (AV
AV
will be derived directly from V
There are a number of ways to reliably provide power to the PLLs, but the recommended solution is to
provide five independent filter circuits as illustrated in
providing independent filters to each PLL, the opportunity to cause noise injection from one PLL to the
other is reduced.
Freescale Semiconductor
DD
•
•
2, respectively). The AV
T
T
R
P
The platform PLL (AV
input. The frequency ratio between the platform and CLKIN is selected using the platform PLL
ratio configuration bits as described in
The e300 core PLL (AV
frequency ratio between the e300 core clock and the platform clock is selected using the e300 PLL
ratio configuration bits as described in
MPC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 3
J
C
θ
D
System Clocking
PLL Power Supply Filtering
JC
= junction temperature (°C)
= case temperature of the package (°C)
= power dissipation (W)
Experimental Determination of the Junction Temperature with a
Heat Sink
= junction to case thermal resistance (°C/W)
T
J
= T
C
+ (R
θ
JC
DD
DD
× P
DD
DD
1) generates the platform clock from the externally supplied CLKIN
level should always be equivalent to V
D
2) generates the core clock as a slave to the platform clock. The
through a low frequency filter scheme such as the following.
)
Section 22.1, “System PLL Configuration.”
Section 22.2, “Core PLL Configuration.”
Figure
54, one to each of the five AV
DD
, and preferably these voltages
System Design Information
DD
pins. By
DD
1,
89