PIC12F1822 MICROCHIP [Microchip Technology], PIC12F1822 Datasheet - Page 305

• Manufacturer Part Number: PIC12F1822
• Description: 8/14-Pin Flash Microcontrollers with nanoWatt XLP Technology
• Manufacturer: MICROCHIP [Microchip Technology]

25.4.2.3
The operation of the Synchronous Master and Slave
modes is identical (Section 25.4.1.5 “Synchronous
Master Reception”), with the following exceptions:
• Sleep
• CREN bit is always set, therefore the receiver is
• SREN bit, which is a “don’t care” in Slave mode
A character may be received while in Sleep mode by
setting the CREN bit prior to entering Sleep. Once the
word is received, the RSR register will transfer the data
to the RCREG register. If the RCIE enable bit is set, the
interrupt generated will wake the device from Sleep
and execute the next instruction. If the GIE bit is also
set, the program will branch to the interrupt vector.
TABLE 25-10: SUMMARY OF REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE
 2010 Microchip Technology Inc.
BAUDCON
INTCON
PIE1
PIR1
RCREG
RCSTA
TRISC
TXSTA
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used for Synchronous Slave Reception.
Note 1:
never Idle
Name
(1)
*
Page provides register information.
PIC16F/LF1823 only.
EUSART Synchronous Slave
Reception
TMR1GIE
TMR1GIF
ABDOVF
CSRC
SPEN
Bit 7
RECEPTION
GIE
—
RCIDL
ADIE
PEIE
ADIF
Bit 6
RX9
TX9
—
TMR0IE
TRISC5
SREN
TXEN
RCIE
RCIF
Bit 5
—
EUSART Receive Data Register
PIC12F/LF1822/16F/LF1823
TRISC4
Preliminary
CREN
SCKP
SYNC
INTE
Bit 4
TXIE
TXIF
TRISC3
SSP1IE
SSP1IF
ADDEN
SENDB
BRG16
IOCIE
25.4.2.4
1.
2.
3.
4.
5.
6.
7.
8.
9.
Bit 3
Set the SYNC and SPEN bits and clear the
CSRC bit.
Clear the ANSEL bit for both the CK and DT pins
(if applicable).
If interrupts are desired, set the RCIE bit of the
PIE1 register and the GIE and PEIE bits of the
INTCON register.
If 9-bit reception is desired, set the RX9 bit.
Set the CREN bit to enable reception.
The RCIF bit will be set when reception is
complete. An interrupt will be generated if the
RCIE bit was set.
If 9-bit mode is enabled, retrieve the Most
Significant bit from the RX9D bit of the RCSTA
register.
Retrieve the 8 Least Significant bits from the
receive FIFO by reading the RCREG register.
If an overrun error occurs, clear the error by
either clearing the CREN bit of the RCSTA
register or by clearing the SPEN bit which resets
the EUSART.
TMR0IF
CCP1IE
CCP1IF
TRISC2
BRGH
FERR
Bit 2
—
Synchronous Slave Reception
Set-up:
TMR2IE
TMR2IF
TRISC1
OERR
TRMT
WUE
Bit 1
INTF
TMR1IE
TMR1IF
TRISC0
ABDEN
IOCIF
RX9D
TX9D
Bit 0
DS41413A-page 305
Register
on Page
284*
290
289
125
288
89
90
92