PIC12F1822 MICROCHIP [Microchip Technology], PIC12F1822 Datasheet - Page 201
PIC12F1822
Manufacturer Part Number
PIC12F1822
Description
8/14-Pin Flash Microcontrollers with nanoWatt XLP Technology
Manufacturer
MICROCHIP [Microchip Technology]
Datasheet
1.PIC12F1822.pdf
(398 pages)
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23.1.5
Capture mode depends upon the Timer1 module for
proper operation. There are two options for driving the
Timer1 module in Capture mode. It can be driven by the
instruction clock (F
When Timer1 is clocked by F
increment during Sleep. When the device wakes from
Sleep, Timer1 will continue from its previous state.
Capture mode will operate during Sleep when Timer1
is clocked by an external clock source.
TABLE 23-2:
2010 Microchip Technology Inc.
CCP1CON
CCPR1L
CCPR1H
INTCON
PIE1
PIE2
PIR1
PIR2
T1CON
T1GCON
TMR1L
TMR1H
TRISA
TRISC
Legend: — = Unimplemented location, read as ‘0’. Shaded cells are not used by Capture mode.
Note 1:
Name
(1)
PIC16F/LF1823 only.
CAPTURE DURING SLEEP
Capture/Compare/PWM Register x Low Byte (LSB)
Capture/Compare/PWM Register x High Byte (MSB)
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
TMR1GIE
TMR1GIF
TMR1GE
OSFIE
OSFIF
Bit 7
GIE
TMR1CS<1:0>
—
—
OSC
SUMMARY OF REGISTERS ASSOCIATED WITH CAPTURE
P1M<1:0>
/4), or by an external clock source.
T1GPOL
C2IE
C2IF
ADIE
Bit 6
PEIE
ADIF
—
—
(1)
(1)
OSC
/4, Timer1 will not
TMR0IE
TRISA5
TRISC5
T1GTM
RCIE
RCIF
Bit 5
C1IE
C1IF
T1CKPS<1:0>
DC1B<1:0>
PIC12F/LF1822/16F/LF1823
T1GSPM T1GGO/DONE
TRISC4
TRISA4
INTE
TXIE
EEIE
Bit 4
TXIF
EEIF
Preliminary
T1OSCEN
TRISC3
SSP1IE
SSP1IF
TRISA3
BCL1IE
BCL1IF
IOCIE
Bit 3
T1SYNC
T1GVAL
TMR0IF
CCP1IE
CCP1IF
TRISC2
TRISA2
CCP1M<3:0>
Bit 2
—
—
TMR2IE
TMR2IF
TRISA1
TRISC1
Bit 1
INTF
—
—
—
T1GSS<1:0>
TMR1ON
TMR1IE
TMR1IF
TRISA0
TRISC0
IOCIF
Bit 0
DS41413A-page 201
—
—
Register
on Page
221
200
200
180
181
172
172
121
125
89
90
91
92
93
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