KSZ8895 INFINEON [Infineon Technologies AG], KSZ8895 Datasheet - Page 97

• Manufacturer Part Number: KSZ8895
• Description: Integrated 5-Port 10/100 Managed Ethernet Switch with MII/RMII interface
• Manufacturer: INFINEON [Infineon Technologies AG]

Micrel, Inc.
MIIM Registers
All the registers defined in this section can be also accessed via the SPI interface. Note: different mapping
mechanisms used for MIIM and SPI. The “PHYAD” defined in IEEE is assigned as “0x1” for Port 1, “0x2” for Port 2,
“0x3” for Port 3, “0x4” for Port 4, and “0x5” for Port 5. The “REGAD” supported are 0x0-0x5 (0h-5h), 0x1D (1dh) and
0x1F (1fh).
January 2011
Address
Register 0h: MII Control
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Register 1h: MII Status
15
14
13
Name
Soft Reset
Loop Back
Force 100
AN Enable
Power Down
PHY Isolate
Restart AN
Force Full Duplex
Collision Test
Reserved
Hp_mdix
Force MDI
Disable Auto MDI/MDI-X
Disable far End fault
Disable Transmit
Disable LED
T4 Capable
100 Full Capable
100 Half Capable
1, 100BASE-TX full-duplex capable.
Description
1, PHY soft reset.
0, Normal operation.
1 = Perform MAC loopback, loop back path as follows:
Assume the loop-back is at Port 1 MAC, Port 2 is the
monitor port.
port 3, 4, 5
Ports 3, 4, 5 respectively
perform MAC loopback on Ports 3, 4, 5 respectively.
0 = Normal Operation.
1, 100Mbps.
0, 10Mbps.
1, Auto-negotiation enabled.
0, Auto-negotiation disabled.
1, Power down.
0, Normal operation.
1, Electrical PHY isolation of PHY from Tx+/Tx-.
0, Normal operation.
1, Restart Auto-negotiation.
0, Normal operation.
1, Full duplex.
0, Half duplex.
Not supported.
1 = HP Auto MDI/MDI-X mode
0 = Micrel Auto MDI/MDI-X mode
1, Force MDI.
0, Normal operation.
1, Disable auto MDI/MDI-X.
0, Normal operation.
1, Disable far end fault detection.
0, Normal operation.
1, Disable transmit.
0, Normal operation.
1, Disable LED.
0, Normal operation.
0, Not 100 BASET4 capable.
0, Not capable of 100BASE-TX full-duplex.
1, 100BASE-TX half-duplex capable.
0, Not 100BASE-TX half-duplex capable.
Setting address ox3,4,5 reg. 0, bit 14 = ‘1’ will
Port 1 MAC Loopback (Port 1 reg. 0, bit 14 = ‘1’)
Start: RXP2/RXM2 (Port 2). Can also start from
Loopback: MAC/PHY interface of Port 1’s MAC
End: TXP2/TXM2 (Port 2). Can also end at
97
Mode
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
(SC)
RO
RO
RO
RO
RO
KSZ8895MQ/RQ/FMQ
M9999-012011-1.2
Default
0
0
1
1
0
0
0
0
0
0
1
0
0
0
0
0
0
1
1