KSZ8895 INFINEON [Infineon Technologies AG], KSZ8895 Datasheet - Page 49

• Manufacturer Part Number: KSZ8895
• Description: Integrated 5-Port 10/100 Managed Ethernet Switch with MII/RMII interface
• Manufacturer: INFINEON [Infineon Technologies AG]

Micrel, Inc.
To configure the KSZ8895MQ/RQ/FMQ with a pre-configured EEPROM use the following steps:
1. At the board level, connect pin 110 on the KSZ8895MQ/RQ/FMQ to the SCL pin on the EEPROM. Connect pin
2. Set the input signals PS[1:0] (pins 113 and 114, respectively) to “00.” This puts the KSZ8895MQ/RQ/FMQ serial
3. Be sure the board-level reset signal is connected to the KSZ8895MQ/RQ/FMQ reset signal on pin 115 (RST_N).
4. Program the contents of the EEPROM before placing it on the board with the desired configuration data. Note
5. Place EEPROM on the board and power up the board. Assert the active-low board level reset to RST_N on the
Note: For proper operation, make sure that pin 47 (PWRDN_N) is not asserted during the reset operation.
SPI Slave Serial Bus Configuration
The KSZ8895MQ/RQ/FMQ can also act as a SPI slave device. Through the SPI, the entire feature set can be
enabled, including “VLAN,” “IGMP snooping,” “MIB counters,” etc. The external master device can access any
register from Register 0 to Register 127 randomly. The system should configure all the desired settings before
enabling the switch in the KSZ8895MQ/RQ/FMQ. To enable the switch, write a "1" to Register 1 bit 0.
Two standard SPI commands are supported (00000011 for “READ DATA,” and 00000010 for “WRITE DATA”). To
speed configuration time, the KSZ8895MQ/RQ/FMQ also supports multiple reads or writes. After a byte is written to
or read from the KSZ8895MQ/RQ/FMQ, the internal address counter automatically increments if the SPI Slave
Select Signal (SPIS_N) continues to be driven low. If SPIS_N is kept low after the first byte is read, the next byte at
the next address will be shifted out on SPIQ. If SPIS_N is kept low after the first byte is written, bits on the Master
Out Slave Input (SPID) line will be written to the next address. Asserting SPIS_N high terminates a read or write
operation. This means that the SPIS_N signal must be asserted high and then low again before issuing another
command and address. The address counter wraps back to zero once it reaches the highest address. Therefore the
entire register set can be written to or read from by issuing a single command and address.
The default SPI clock speed is 12.5MHz. The KSZ8895MQ/RQ/FMQ is able to support a SPI bus up to 25MHz (set
register 12 bit [5:4]=0x10). A high performance SPI master is recommended to prevent internal counter overflow.
January 2011
111 on the KSZ8895MQ/RQ/FMQ to the SDA pin on the EEPROM.
bus configuration into I
that the first byte in the EEPROM must be “95” for the loading to occur properly. If this value is not correct, all
other data will be ignored.
KSZ8895MQ/RQ/FMQ. After the reset is de-asserted, the KSZ8895MQ/RQ/FMQ will begin reading configuration
data from the EEPROM. The configuration access time (t
RST_N
SCL
SDA
Figure 8. KSZ8895MQ/RQ/FMQ EEPROM Configuration Timing Diagram
2
C master mode.
49
prgm
) is less than 30ms.
t prgm <30 ms
....
....
....
KSZ8895MQ/RQ/FMQ
M9999-012011-1.2