KSZ8851-16MLLJ_10 MICREL [Micrel Semiconductor], KSZ8851-16MLLJ_10 Datasheet - Page 72

• Manufacturer Part Number: KSZ8851-16MLLJ_10
• Description: Single-Port Ethernet MAC Controller with 8-Bit or 16-Bit Non-PCI Interface
• Manufacturer: MICREL [Micrel Semiconductor]

PHY 1 MII-Register Basic Status Register (0xE6 – 0xE7): P1MBSR
This register contains the MII register status for the chip function.
PHY 1 PHY ID Low Register (0xE8 – 0xE9): PHY1ILR
This register contains the PHY ID (low) for the chip.
March 2010
Micrel, Inc.
Bit
15
14
13
12
11
10-7
6
5
4
3
2
1
0
Bit
15-0
Default
0
1
1
1
1
0x0
0
0
0
1
0
0
0
Default
0x1430
R/W
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
R/W
RO
Description
T4 Capable
1 = 100 BASE-T4 capable.
0 = not 100 BASE-T4 capable.
100 Full Capable
1 = 100BASE-TX full-duplex capable.
0 = not 100BASE-TX full duplex.capable.
100 Half Capable
1= 100BASE-TX half-duplex capable.
0= not 100BASE-TX half-duplex capable.
10 Full Capable
1 = 10BASE-T full-duplex capable.
0 = not 10BASE-T full-duplex capable.
10 Half Capable
1 = 10BASE-T half-duplex capable.
0 = not 10BASE-T half-duplex capable.
Reserved.
Preamble suppressed
Not supported.
AN Complete
1 = auto-negotiation complete.
0 = auto-negotiation not completed.
Reserved
AN Capable
1 = auto-negotiation capable.
0 = not auto-negotiation capable.
Link Status
1 = link is up; 0 = link is down.
Jabber test
Not supported.
Extended Capable
1 = extended register capable.
0 = not extended register capable.
Description
PHYID Low
Low order PHYID bits.
72
Bit is same as:
Bit 6 in P1SR
Bit 5 in P1SR
M9999-030210-1.0
KSZ8851-16MLLJ