KSZ8851-16MLLJ_10 MICREL [Micrel Semiconductor], KSZ8851-16MLLJ_10 Datasheet - Page 33

• Manufacturer Part Number: KSZ8851-16MLLJ_10
• Description: Single-Port Ethernet MAC Controller with 8-Bit or 16-Bit Non-PCI Interface
• Manufacturer: MICREL [Micrel Semiconductor]

Receive Queue (RXQ) Frame Format
The frame format for the receive queue is shown in Table 9. The first word contains the status information for the frame
received. The second word is the total number of bytes of the RX frame. Following that is the packet data area. The
packet data area holds the frame itself. It includes the CRC checksum.
Frame Receiving Path Operation in RXQ
This section describes the typical register settings for receiving packets from KSZ8851-16MLLJ to host processor with
generic bus interface. User can use the default value for most of the receive registers. The following Table 10 describes
all registers which need to be set and used for receiving single or multiple frames.
March 2010
Micrel, Inc.
Packet Memory
Address Offset
0
2
4 - up
Table 9. Frame Format for Receive Queue
Bit 15
2
Status Word
(High byte and low byte need to swap in Big-Endian
mode. Also see description in RXFHSR register)
Byte Count
(High byte and low byte need to swap in Big-Endian
mode. Also see description in RXFHBCR register)
Receive Packet Data
(maximum size is 2000)
nd
Byte
33
1
st
Bit 0
Byte
M9999-030210-1.0
KSZ8851-16MLLJ