KSZ8851-16MLLJ_10 MICREL [Micrel Semiconductor], KSZ8851-16MLLJ_10 Datasheet - Page 60

• Manufacturer Part Number: KSZ8851-16MLLJ_10
• Description: Single-Port Ethernet MAC Controller with 8-Bit or 16-Bit Non-PCI Interface
• Manufacturer: MICREL [Micrel Semiconductor]

RXQ Command Register (0x82 – 0x83): RXQCR
This register is programmed by the Host CPU to issue DMA read or write command to the RXQ and TXQ. This register
also is used to control all RX thresholds enable and status.
March 2010
Micrel, Inc.
Bit
15-13
12
11
10
9
8
7
6
5
4
3
-
-
-
-
0x0
-
0x0
0x0
0x0
0x0
0x0
Default Value
R/W
RW
RO
RO
RO
RW
RW
RW
RW
RW
RW
WO
Description
Reserved.
RXDTTS RX Duration Timer Threshold Status
When this bit is set, it indicates that RX interrupt is due to the time start at first received
frame in RXQ buffer exceeds the threshold set in RX Duration Timer Threshold Register
(0x8C, RXDTT).
This bit will be updated when write 1 to bit 13 in ISR register.
RXDBCTS RX Data Byte Count Threshold Status
When this bit is set, it indicates that RX interrupt is due to the number of received bytes in
RXQ buffer exceeds the threshold set in RX Data Byte Count Threshold Register (0x8E,
RXDBCT).
This bit will be updated when write 1 to bit 13 in ISR register.
RXFCTS RX Frame Count Threshold Status
When this bit is set, it indicates that RX interrupt is due to the number of received frames
in RXQ buffer exceeds the threshold set in RX Frame Count Threshold Register (0x9C,
RXFCT).
This bit will be updated when write 1 to bit 13 in ISR register.
RXIPHTOE RX IP Header Two-Byte Offset Enable
When this bit is written as 1, the KSZ8851-16MLLJ will enable to add two bytes before
frame header in order for IP header inside the frame contents to be aligned with double
word boundary to speed up software operation.
Reserved.
RXDTTE RX Duration Timer Threshold Enable
When this bit is written as 1, the KSZ8851-16MLLJ will enable RX interrupt (bit 13 in ISR)
when the time start at first received frame in RXQ buffer exceeds the threshold set in RX
Duration Timer Threshold Register (0x8C, RXDTT).
RXDBCTE RX Data Byte Count Threshold Enable
When this bit is written as 1, the KSZ8851-16MLLJ will enable RX interrupt (bit 13 in ISR)
when the number of received bytes in RXQ buffer exceeds the threshold set in RX Data
Byte Count Threshold Register (0x8E, RXDBCT).
RXFCTE RX Frame Count Threshold Enable
When this bit is written as 1, the KSZ8851-16MLLJ will enable RX interrupt (bit 13 in ISR)
when the number of received frames in RXQ buffer exceeds the threshold set in RX
Frame Count Threshold Register (0x9C, RXFCT).
ADRFE Auto-Dequeue RXQ Frame Enable
When this bit is written as 1, the KSZ8851-16MLLJ will automatically enable RXQ frame
buffer dequeue. The read pointer in RXQ frame buffer will be automatically adjusted to
next received frame location after current frame is completely read by the host.
SDA Start DMA Access
When this bit is written as 1, the KSZ8851-16MLLJ allows a DMA operation from the host
CPU to access either read RXQ frame buffer or write TXQ frame buffer with CSN and
RDN or WRN signals while the CMD pin is low. All registers access are disabled except
this register during this DMA operation.
This bit must be set to 0 when DMA operation is finished in order to access the rest of
registers.
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M9999-030210-1.0
KSZ8851-16MLLJ