SAA7124WP PHILIPS [NXP Semiconductors], SAA7124WP Datasheet - Page 24

• Manufacturer Part Number: SAA7124WP
• Description: Digital Video Encoder ECO-DENC
• Manufacturer: PHILIPS [NXP Semiconductors]

Philips Semiconductors
Table 20 Subaddress 6C and 6D
Table 21 Subaddress 6D
Table 22 Subaddress 6E
Table 23 Logic levels and function of PHRES
Table 24 Logic levels and function of FLC
1996 Nov 07
HTRIG
VTRIG
SBLBN
PHRES
FLC
DATA BYTE
DATA BYTE
DATA BYTE
Digital Video Encoder (ECO-DENC)
PHRES1
FLC1
0
0
1
1
0
0
1
1
DATA BYTE
DATA BYTE
sets the horizontal trigger phase related to signal on RCV1 or RCV2 input (or to decoded “CCIR 656”
data)
sets the vertical trigger phase related to signal on RCV1 input (or to decoded “CCIR 656” data)
LOGIC LEVEL
values above 1715 (FISE = 1) or 1727 (FISE = 0) are not allowed
increasing HTRIG decreases delays of all internally generated timing signals
reference mark: analog output horizontal sync (leading slope) coincides with active edge of RCV
used for triggering at HTRIG = tbfH (tbfH)
increasing VTRIG decreases delays of all internally generated timing signals, measured in half lines
variation range of VTRIG = 0 to 31 (1FH)
PHRES0
FLC0
0
1
0
1
0
1
0
1
0
1
vertical blanking is defined by programming of FAL and LAL; default after reset
vertical blanking is forced in accordance with “CCIR 624” (50 Hz) or “RS170A”
(60 Hz)
selects the phase reset mode of the colour subcarrier generator; see Table 23
field length control; see Table 24
no reset or reset via RTCI from SAA7111 if bit RTCE = 1; default after reset
reset every two lines
reset every eight fields
reset every four fields
interlaced 312.5 lines/field at 50 Hz, 262.5 lines/field at 60 Hz; default after reset
non-interlaced 312 lines/field at 50 Hz, 262 lines/field at 60 Hz
non-interlaced 313 lines/field at 50 Hz, 263 lines/field at 60 Hz
non-interlaced 313 lines/field at 50 Hz, 263 lines/field at 60 Hz
24
DESCRIPTION
DESCRIPTION
DESCRIPTION
FUNCTION
FUNCTION
SAA7124; SAA7125
Preliminary specification