SAA7124WP PHILIPS [NXP Semiconductors], SAA7124WP Datasheet - Page 2

• Manufacturer Part Number: SAA7124WP
• Description: Digital Video Encoder ECO-DENC
• Manufacturer: PHILIPS [NXP Semiconductors]

Philips Semiconductors
FEATURES
ORDERING INFORMATION
Note
1. LQFP64 package for V1 devices only.
1996 Nov 07
SAA7124WP;
SAA7125WP
SAA7124HZ;
SAA7125HZ
SAA7124H;
SAA7125H
Monolithic CMOS 5 V device
Digital PAL/NTSC encoder
System pixel frequency 13.5 MHz
Accepts MPEG decoded data on 8-bit wide input port.
Input data format Cb, Y, Cr etc. “(CCIR 656)”
Four DACs for CVBS (10-bit resolution), RGB (9-bit
resolution) operating at 27 MHz; RGB sync on CVBS
Optionally 2 times CVBS and Y, C (all 10-bit resolution)
available simultaneously
Closed captioning encoding
On-chip YUV to RGB dematrix optionally to be
by-passed for Cr, Y, Cb output on RGB DACs
Fast I
Encoder can be master or slave
Programmable horizontal and vertical input
synchronization phase, via input pins or auxiliary codes
at MP data port
Programmable horizontal sync output phase
Internal 100/75 Colour Bar Generator (CBG)
Macrovision Pay-per-View copy protection system as
option, also partly used for RGB output.
This applies to SAA7124 only. The device is protected
by USA patent numbers 4631603, 4577216 and
4819098 and other intellectual property rights. Use of
the Macrovision anti-copy process in the device is
licensed for non-commercial home use only.
Reverse engineering or disassembly is prohibited.
Please contact your nearest Philips Semiconductor
sales office for more information
Digital Video Encoder (ECO-DENC)
NUMBER
TYPE
2
C-bus control port (400 kHz)
PLCC84
LQFP64
QFP80
NAME
plastic leaded chip carrier; 84 leads
plastic low profile quad flat package; 64 leads; body 10
plastic quad flat package; 80 leads (lead length 2.35 mm);
body 14
20
2.8 mm
2
DESCRIPTION
GENERAL DESCRIPTION
The SAA7124; SAA7125 encodes digital YUV video data
to an NTSC or PAL CVBS plus RGB or alternatively to
S-Video and CVBS output.
Optionally, the YUV to RGB dematrix can be by-passed
providing the digital-to-analog converted Cb, Y, Cr signals
instead of RGB.
The circuit accepts CCIR compatible YUV data with
720 active pixels per line in 4 : 2 : 2 multiplexed formats,
for example MPEG decoded data.
It includes a sync/clock generator and on-chip
Digital-to-Analog Converters (DACs).
PACKAGE
Controlled rise and fall times of output syncs and
blanking
Down-mode of DACs
LQFP64 (V1 devices only), QFP80 or PLCC84
package.
(1)
SAA7124; SAA7125
10
Preliminary specification
1.4 mm
SOT189-2
SOT314-2
SOT318-3
VERSION