ADSP-BF531WBBCZ-4A AD [Analog Devices], ADSP-BF531WBBCZ-4A Datasheet - Page 6

• Manufacturer Part Number: ADSP-BF531WBBCZ-4A
• Description: Blackfin Embedded Processor
• Manufacturer: AD [Analog Devices]

ADSP-BF531/ADSP-BF532
The asynchronous memory controller can be programmed to
control up to four banks of devices with very flexible timing
parameters for a wide variety of devices. Each bank occupies a
1M byte segment regardless of the size of the devices used, so
that these banks will only be contiguous if each is fully popu-
lated with 1M byte of memory.
I/O Memory Space
Blackfin processors do not define a separate I/O space. All
resources are mapped through the flat 32-bit address space.
On-chip I/O devices have their control registers mapped into
memory mapped registers (MMRs) at addresses near the top of
the 4G byte address space. These are separated into two smaller
blocks, one of which contains the control MMRs for all core
functions, and the other of which contains the registers needed
for setup and control of the on-chip peripherals outside of the
core. The MMRs are accessible only in supervisor mode and
appear as reserved space to on-chip peripherals.
Booting
The ADSP-BF531/ADSP-BF532 processor contains a small boot
kernel, which configures the appropriate peripheral for booting.
If the ADSP-BF531/ADSP-BF532 processor is configured to
DA1
DA0
LD1
LD0
SD
32
32
32
32
32
R1.H
R0.H
R7.H
R6.H
R3.H
R2.H
R5.H
R4.H
RAB
32
R0.L
R7.L
R2.L
R1.H
I3
R6.L
R5.L
R4.L
R3.L
I2
I1
I0
32
L3
L2
L1
L0
32
BARREL
SHIFTER
B3
B2
B1
B0
8
Rev. D | Page 6 of 60 | August 2006
ADDRESS ARITHMETIC UNIT
32
M3
M2
M1
Figure 2. Blackfin Processor Core
M0
A0
DATA ARITHMETIC UNIT
16
40
32
DAG1
8
40
40
boot from boot ROM memory space, the processor starts exe-
cuting from the on-chip boot ROM. For more information, see
Booting Modes on Page
Event Handling
The event controller on the ADSP-BF531/ADSP-BF532 proces-
sor handles all asynchronous and synchronous events to the
processor. The ADSP-BF531/ADSP-BF532 processor provides
event handling that supports both nesting and prioritization.
Nesting allows multiple event service routines to be active
simultaneously. Prioritization ensures that servicing of a higher
priority event takes precedence over servicing of a lower priority
event. The controller provides support for five different types
of events:
8
• Emulation – An emulation event causes the processor to
• Reset – This event resets the processor.
• Nonmaskable Interrupt (NMI) – The NMI event can be
DAG0
enter emulation mode, allowing command and control of
the processor via the JTAG interface.
generated by the software watchdog timer or by the NMI
input signal to the processor. The NMI event is frequently
used as a power-down indicator to initiate an orderly shut-
down of the system.
16
40
A1
ASTAT
SP
P5
P3
P2
P1
P0
FP
P4
8
32
PREG
14.
LOOP BUFFER
SEQUENCER
DECODE
CONTROL
ALIGN
UNIT