ADSP-BF531WBBCZ-4A AD [Analog Devices], ADSP-BF531WBBCZ-4A Datasheet - Page 28
ADSP-BF531WBBCZ-4A
Manufacturer Part Number
ADSP-BF531WBBCZ-4A
Description
Blackfin Embedded Processor
Manufacturer
AD [Analog Devices]
Datasheet
1.ADSP-BF531WBBCZ-4A.pdf
(60 pages)
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ADSP-BF531/ADSP-BF532
External Port Bus Request and Grant Cycle Timing
Table 19
bus grant operations.
Table 19. External Port Bus Request and Grant Cycle Timing
Parameter
Timing Requirements
t
t
Switching Characteristics
t
t
t
t
t
t
BS
BH
SD
SE
DBG
EBG
DBH
EBH
BR Asserted to CLKOUT High Setup
CLKOUT High to BR Deasserted Hold Time
CLKOUT Low to xMS, Address, and RD/WR Disable
CLKOUT Low to xMS, Address, and RD/WR Enable
CLKOUT High to BG High Setup
CLKOUT High to BG Deasserted Hold Time
CLKOUT High to BGH High Setup
CLKOUT High to BGH Deasserted Hold Time
and
CLKOUT
ADDR19-1
ABE1-0
Figure 14
AMSx
AWE
BGH
ARE
BG
BR
describe external port bus request and
t
BS
Figure 14. External Port Bus Request and Grant Cycle Timing
Rev. D | Page 28 of 60 | August 2006
t
BH
t
t
t
SD
SD
SD
t
t
DBG
DBH
V
Min
4.6
1.0
DDEXT
= 1.8 V V
Max
4.5
4.5
4.6
4.6
4.6
4.6
t
t
EBG
EBH
Min
4.6
0.0
DDEXT
= 2.5 V/3.3 V
t
t
t
SE
SE
SE
Max
4.5
4.5
3.6
3.6
3.6
3.6
Unit
ns
ns
ns
ns
ns
ns
ns
ns
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