ADSP-BF531WBBCZ-4A AD [Analog Devices], ADSP-BF531WBBCZ-4A Datasheet - Page 23

• Manufacturer Part Number: ADSP-BF531WBBCZ-4A
• Description: Blackfin Embedded Processor
• Manufacturer: AD [Analog Devices]

TIMING SPECIFICATIONS
Table 12
the ADSP-BF531/ADSP-BF532 processor clocks. Take care in
selecting MSEL, SSEL, and CSEL ratios so as not to exceed the
maximum core clock and system clock as described in
Table 12. Core Clock Requirements
1
Table 13. Phase-Locked Loop Operating Conditions
Table 14. Maximum SCLK Conditions
1
Parameter
t
t
t
t
t
See
Parameter
f
Parameter
MBGA/PBGA
f
f
LQFP
f
f
t
VCO
SCLK
SCLK
SCLK
SCLK
SCLK
CCLK
CCLK
CCLK
CCLK
CCLK
Operating Conditions on Page
(= 1/f
Voltage Controlled Oscillator (VCO) Frequency
Core Cycle Period (V
Core Cycle Period (V
Core Cycle Period (V
Core Cycle Period (V
Core Cycle Period (V
SCLK
through
) must be greater than or equal to t
1
Table 14
CLKOUT/SCLK Frequency (V
CLKOUT/SCLK Frequency (V
CLKOUT/SCLK Frequency (V
CLKOUT/SCLK Frequency (V
describe the timing requirements for
DDINT
DDINT
DDINT
DDINT
DDINT
20.
=1.14 V minimum)
=1.045 V minimum)
=0.95 V minimum)
=0.85 V minimum)
=0.8 V )
CCLK
.
DDINT
DDINT
DDINT
DDINT
Rev. D | Page 23 of 60 | August 2006
1.14 V)
1.14 V)
1.14 V)
1.14 V)
Absolute
Maximum Ratings on Page
lator (VCO) operating frequencies described in
Table 13
Min
2.50
3.00
3.39
Min
50
V
100
100
100
83
DDEXT
T
= 1.8 V
describes phase-locked loop operating conditions.
JUNCTION
= 125°C
Max
Max
Maximum f
ADSP-BF531/ADSP-BF532
V
133
100
133
83
DDEXT
= 2.5 V
22, and the voltage controlled oscil-
CCLK
Min
2.50
2.75
3.00
3.57
4.00
All
1
Other T
V
133
100
133
83
DDEXT
Max
= 3.3 V
JUNCTION
Table
13.
Unit
ns
ns
ns
ns
ns
Unit
MHz
Unit
MHz
MHz
MHz
MHz