ADSP-BF531WBBCZ-4A AD [Analog Devices], ADSP-BF531WBBCZ-4A Datasheet - Page 37

• Manufacturer Part Number: ADSP-BF531WBBCZ-4A
• Description: Blackfin Embedded Processor
• Manufacturer: AD [Analog Devices]

Serial Peripheral Interface (SPI) Port
—Master Timing
Table 25
Table 25. Serial Peripheral Interface (SPI) Port—Master Timing
Parameter
Timing Requirements
t
Switching Characteristics
t
t
t
t
t
t
t
t
t
SSPIDM
SDSCIM
SPICHM
SPICLM
SPICLK
HDSM
SPITDM
DDSPIDM
HDSPIDM
HSPIDM
CPHA = 0
CPHA = 1
and
Data Input Valid to SCK Edge (Data Input Setup)
SCK Sampling Edge to Data Input Invalid
SPISELx Low to First SCK Edge (x=0 or x=1)
Serial Clock High Period
Serial Clock Low Period
Serial Clock Period
Last SCK Edge to SPISELx High (x=0 or x=1)
Sequential Transfer Delay
SCK Edge to Data Out Valid (Data Out Delay)
SCK Edge to Data Out Invalid (Data Out Hold)
Figure 22
(OUTPUT)
(INPUT)
(INPUT)
(OUTPUT)
(OUTPUT)
(CPOL = 0)
(CPOL = 1)
SPISELx
(OUTPUT)
(OUTPUT)
MISO
MISO
MOSI
MOSI
SCK
SCK
describe SPI port master operations.
t
SSPIDM
t
SDSCIM
MSB VALID
t
SSPIDM
Figure 22. Serial Peripheral Interface (SPI) Port—Master Timing
MSB
t
t
SPICHM
SPICLM
MSB VALID
t
HSPIDM
Rev. D | Page 37 of 60 | August 2006
t
t
t
DDSPIDM
MSB
SPICLM
SPICHM
t
HSPIDM
t
DDSPIDM
t
HDSPIDM
LSB VALID
t
t
SSPIDM
SPICLK
t
HDSPIDM
LSB VALID
LSB
V
Min
8.5
–1.5
2t
2t
2t
4t
2t
2t
0
–1.0
ADSP-BF531/ADSP-BF532
DDEXT
t
SCLK
SCLK
SCLK
SCLK
SCLK
SCLK
HDSM
LSB
t
HSPIDM
–1.5
–1.5
–1.5
–1.5
–1.5
–1.5
= 1.8 V
Max Min
6
+4.0 –1.0
t
SPITDM
V
7.5
–1.5
2t
2t
2t
4t
2t
2t
0
DDEXT
SCLK
SCLK
SCLK
SCLK
SCLK
SCLK
–1.5
–1.5
–1.5
–1.5
–1.5
–1.5
= 2.5 V/3.3 V
Max
6
+4.0
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns