ADSP-BF522 AD [Analog Devices], ADSP-BF522 Datasheet - Page 46

• Manufacturer Part Number: ADSP-BF522
• Description: Blackfin Embedded Processor
• Manufacturer: AD [Analog Devices]

ADSP-BF522/523/524/525/526/527
Parallel Peripheral Interface Timing
Table 36
Figure 25 on Page 51
operations.
Table 36. Parallel Peripheral Interface Timing
1
Parameter
Timing Requirements
t
t
Timing Requirements - GP Input and Frame Capture Modes
t
t
t
t
Switching Characteristics - GP Output and Frame Capture Modes
t
t
t
t
PPI_CLK frequency cannot exceed f
PCLKW
PCLK
SFSPE
HFSPE
SDRPE
HDRPE
DFSPE
HOFSPE
DDTPE
HDTPE
PPI_CLK
POLC = 0
PPI_CLK
POLC = 1
PPI_FS1
PPI_FS2
PPI_DATA
and
POLS = 1
POLS = 0
POLS = 1
POLS = 0
Figure 19 on Page
PPI_CLK Width
PPI_CLK Period
External Frame Sync Setup Before PPI_CLK
(Nonsampling Edge for Rx, Sampling Edge for Tx)
External Frame Sync Hold After PPI_CLK
Receive Data Setup Before PPI_CLK
Receive Data Hold After PPI_CLK
Internal Frame Sync Delay After PPI_CLK
Internal Frame Sync Hold After PPI_CLK
Transmit Data Delay After PPI_CLK
Transmit Data Hold After PPI_CLK
describe parallel peripheral interface
SCLK
t
46,
SFSPE
/2
1
1
Figure 23 on Page
DATA0 IS
SAMPLED
t
HFSPE
Figure 19. PPI GP Rx Mode with External Frame Sync Timing
Rev. PrG | Page 46 of 80 | February 2009
50, and
t
SDRPE
DATA1 IS
SAMPLED
t
HDRPE
Min
25.0
6.4
6.7
1.0
3.5
1.5
1.7
1.8
ADSP-BF522/524/526
V
1.8 V
DDEXT
Max
8.8
8.8
=
Min
25.0
6.4
6.7
1.0
3.5
1.5
1.7
1.8
2.5/3.3 V
V
DDEXT
Preliminary Technical Data
Max
8.8
8.8
=
Min
15.0
6.0
6.7
1.0
3.5
1.6
1.7
1.8
ADSP-BF523/525/527
V
DDEXT
1.8 V
Max
8.0
8.0
=
15.0
Min
6.0
6.7
1.0
3.5
1.5
1.7
1.8
2.5/3.3 V
V
DDEXT
Max Unit
8.0 ns
8.0 ns
=
ns
ns
ns
ns
ns
ns
ns
ns