ADSP-BF522 AD [Analog Devices], ADSP-BF522 Datasheet - Page 30

• Manufacturer Part Number: ADSP-BF522
• Description: Blackfin Embedded Processor
• Manufacturer: AD [Analog Devices]

ADSP-BF522/523/524/525/526/527
ADSP-BF523/525/527 Clock Related Operating Conditions
Table 15
ADSP-BF523/525/527 processors. Take care in selecting MSEL,
SSEL, and CSEL ratios so as not to exceed the maximum core
clock and system clock (see
locked loop operating conditions.
Table 15. Core Clock (CCLK) Requirements—ADSP-BF523/525/527 Processors—All Speed Grades
1
2
3
Table 16. Phase-Locked Loop Operating Conditions
1
Table 17. ADSP-BF523/525/527 Processors Maximum SCLK Conditions
1
2
3
Parameter
f
f
f
Parameter
f
Parameter
f
f
See the
Applies only to 600 MHz speed grades. See the
Applies only to 533 MHz and 600 MHz speed grades. See the
See the
If either V
f
Rounded number. Actual test specification is SCLK period of 7.5 ns. See
CCLK
CCLK
CCLK
VCO
SCLK
SCLK
SCLK
must be less than or equal to f
Ordering Guide on Page
Ordering Guide on Page
describes the core clock timing requirements for the
DDEXT
or V
DDMEM
Core Clock Frequency (V
Core Clock Frequency (V
Core Clock Frequency (V
Voltage Controlled Oscillator (VCO) Frequency
CLKOUT/SCLK Frequency (V
CLKOUT/SCLK Frequency (V
are operating at 1.8V nominal, f
80.
80.
CCLK
Table
and is subject to additional restrictions for SDRAM interface operation. See
17).
Ordering Guide on Page
Table 16
DDINT
DDINT
DDINT
DDINT
DDINT
describes phase-
SCLK
=1.14 V minimum)
=1.093 V minimum)
= 0.95 V minimum)
Rev. PrG | Page 30 of 80 | February 2009
Ordering Guide on Page
is constrained to 100MHz.
1.14 V)
1.14 V)
80.
Table 34 on Page
2
2
2
3
80.
44.
Internal Regulator Setting
V
DDEXT
Minimum
Nominal
/V
1.20 V
1.15 V
1.0 V
DDMEM
100
100
50
Table 34 on Page
= 1.8 V
1
Preliminary Technical Data
V
1
DDEXT
44.
/V
Speed Grade
Maximum
DDMEM
Nominal
Max
133
600
533
400
100
= 2.5 V/3.3 V
3
1
MHz
MHz
MHz
Unit
Unit
MHz
Unit
MHz
MHz