ADSP-2191 AD [Analog Devices], ADSP-2191 Datasheet - Page 42

• Manufacturer Part Number: ADSP-2191
• Description: DSP Microcomputer
• Manufacturer: AD [Analog Devices]

ADSP-2191M
The output disable time t
t
t
switches to when the output voltage decays –V from the measured
output high or output low voltage. The t
test loads C
Figure 26. Output Enable/Disable
Figure 27. Equivalent Device Loading for AC
Figure 28. Voltage Reference Levels for AC
Output Enable Time
Output pins are considered to be enabled when they have made
a transition from a high impedance state to when they start
driving. The output enable time t
a reference signal reaches a high or low voltage level to when the
output has reached a specified high or low trip point, as shown
in the Output Enable/Disable diagram
pins (such as the data bus) are enabled, the measurement value
is that of the first pin to start driving.
MEASURED
MEASURED
V
V
OL (MEASURED)
REFERENCE
OH (MEASURED)
OUTPUT
INPUT
OUTPUT
SIGNAL
OR
L
Measurements (Includes All Fixtures)
Measurements (Except Output Enable/Disable)
and t
is the interval from when the reference signal
and I
PIN
TO
t
DIS
DECAY
50pF
L
OUTPUT STOPS
, and with –V equal to 0.5 V.
DRIVING
1.5V
DIS
as shown in
t
TEST CONDITIONS CAUSE THIS VOLTAGE
MEASURED
is the difference between
V
V
t
OL (MEASURED)
OH (MEASURED)
DECAY
TO BE APPROXIMATELY 1.5V
ENA
I
HIGH-IMPEDANCE STATE.
I
OL
OH
is the interval from when
DECAY
Figure
(Figure
1.5V
+ V
– V
OUTPUT STARTS
26. The time
is calculated with
26). If multiple
+1.5V
t
1.0V
2.0V
ENA
DRIVING
–42–
Example System Hold Time Calculation
To determine the data output hold time in a particular system,
first calculate t
on page
ADSP-2191M’s output voltage and the input threshold for the
device requiring the hold time. A typical –V will be 0.4 V. C
the total bus capacitance (per data line), and I
or three-state current (per data line). The hold time will be
t
write cycle).
Capacitive Loading
Output delays and holds are based on standard capacitive loads:
50 pF on all pins (see
tions given should be derated by a factor of 1.5 ns/50 pF for loads
other than the nominal value of 50 pF.
show how output rise time varies with capacitance. These figures
also show graphically how output delays and holds vary with load
capacitance. (Note that this graph or derating does not apply to
output disable delays; see
graphs in these figures may not be linear outside the ranges
shown.
Figure 29. Typical Output Rise Time (10%-90%,
Environmental Conditions
The thermal characteristics in which the DSP is operating
influence performance.
Thermal Characteristics
The ADSP-2191M comes in a 144-lead LQFP or 144-lead Ball
Grid Array (mini-BGA) package. The ADSP-2191M is specified
for an ambient temperature (T
formula below.
To ensure that the T
a heatsink and/or an air flow source may be used. A heatsink
should be attached to the ground plane (as close as possible to
the thermal pathways) with a thermal adhesive.
DECAY
30
20
10
41. Choose –V to be the difference between the
40
plus the minimum disable time (i.e., t
0
0
V
Operating Temperature) vs. Load Capacitance
DDEXT
DECAY
T
AMB
50
AMB
= Minimum at Maximum Ambient
using the equation at
Figure
=
LOAD CAPACITANCE – pF
data sheet specification is not exceeded,
Output Disable Time on page
T
CASE
100
30). The delay and hold specifica-
AMB
RISE TIME
–
) as calculated using the
PD
150
Figure 28
Output Disable Time
CA
L
is the total leakage
DATRWH
200
and
Figure 29
41.) The
REV. 0
for the
250
L
is