ADSP-2191 AD [Analog Devices], ADSP-2191 Datasheet - Page 20

• Manufacturer Part Number: ADSP-2191
• Description: DSP Microcomputer
• Manufacturer: AD [Analog Devices]

ADSP-2191M
TIMING SPECIFICATIONS
This section contains timing information for the DSP’s external signals. Use the exact information given. Do not attempt to derive
parameters from the addition or subtraction of other information. While addition or subtraction would yield meaningful results for an
individual device, the values given in this datasheet reflect statistical variations and worst cases. Consequently, parameters cannot be
added meaningfully to derive longer times.
Switching characteristics specify how the processor changes its signals. No control is possible over this timing; circuitry external to the
processor must be designed for compatibility with these signal characteristics. Switching characteristics indicate what the processor
will do in a given circumstance. Switching characteristics can also be used to ensure that any timing requirement of a device connected
to the processor (such as memory) is satisfied.
Timing requirements apply to signals that are controlled by circuitry external to the processor, such as the data input for a read
operation.Timing requirements guarantee that the processor operates correctly with other devices.
Clock In and Clock Out Cycle Timing
Table 9
eral clocks in excess of 160/80 MHz for commercial grade and 140/70 MHz for industrial grade, when the peripheral clock rate is
one-half the core clock rate. If the peripheral clock rate is equal to the core clock rate, the maximum peripheral clock rate is 80 MHz
for both commercial and industrial grade parts. The peripheral clock is supplied to the CLKOUT pins.
When changing from bypass mode to PLL mode, allow 512 HCLK cycles for the PLL to stabilize.
Table 9. Clock In and Clock Out Cycle Timing
1
2
3
CLKOUT jitter can be as great as 8 ns when CLKOUT frequency is less than 20 MHz. For frequencies greater than 20 MHz, jitter is less than 1 ns.
In clock multiplier mode and MSEL6–0 set for 1:1 (or CLKIN=CCLK), t
In bypass mode, t
Parameter
Switching Characteristics
t
t
Timing Requirements
t
t
t
t
t
t
t
t
CKOD
CKO
CK
CKL
CKH
WRST
MSS
MSH
MSD
PFD
and
Figure 8
CK
=t
CLKOUT Delay from CLKIN
CLKOUT Period
CLKIN Period
CLKIN Low Pulse
CLKIN High Pulse
RESET Asserted Pulsewidth Low
MSELx/BYPASS Stable Before RESET Deasserted Setup
MSELx/BYPASS Stable After RESET Deasserted Hold
MSELx/BYPASS Stable After RESET Asserted
Flag Output Disable Time After RESET Asserted
CCLK
describe clock and reset operations. Combinations of CLKIN and clock multipliers must not select core/periph-
.
2, 3
1
–20–
CK
=t CCLK .
Min
0
12.5
10
4.5
4.5
200t
40
1000
CLKOUT
Max
5.8
200
200
10
Unit
ns
ns
ns
ns
ns
ns
µs
ns
ns
ns
REV. 0